TY - JOUR
T1 - Towards the Design of Efficient and Consistent Index Structure with Minimal Write Activities for Non-Volatile Memory
AU - Sha, Edwin Hsing Mean
AU - Jiang, Weiwen
AU - Dong, Hailiang
AU - Ma, Zhulin
AU - Zhang, Runyu
AU - Chen, Xianzhang
AU - Zhuge, Qingfeng
N1 - Publisher Copyright:
© 2017 IEEE.
PY - 2018/3/1
Y1 - 2018/3/1
N2 - Index structures can significantly accelerate the data retrieval operations in data intensive systems, such as databases. Tree structures, such as B+-tree alike, are commonly employed as index structures; however, we found that the tree structure may not be appropriate for Non-Volatile Memory (NVM) in terms of the requirements for high-performance and high-endurance. This paper studies what is the best index structure for NVM-based systems and how to design such index structures. The design of an NVM-friendly index structure faces a lot of challenges. First, in order to prolong the lifetime of NVM, the write activities on NVM should be minimized. To this end, the index structure should be as simple as possible. The index proposed in this paper is based on the simplest data structure, i.e., linked list. Second, the simple structure brings challenges to achieve high-performance data retrieval operations. To overcome this challenge, we design a novel technique by explicitly building up a contiguous virtual address space on the linked list, such that efficient search algorithms can be performed. Third, we need to carefully consider data consistency issues in NVM-based systems, because the order of memory writes may be changed and the data content in NVM may be inconsistent due to write-back effects of CPU cache. This paper devises a novel indexing scheme, called 'Virtual Linear Addressable Buckets' (VLAB). We implement VLAB in a storage engine and plug it into MySQL. Evaluations are conducted on an NVDIMM workstation using YCSB workloads and real-world traces. Results show that write activities of the state-of-the-art indexes are 6.98 times more than ours; meanwhile, VLAB achieves 2.53 times speedup.
AB - Index structures can significantly accelerate the data retrieval operations in data intensive systems, such as databases. Tree structures, such as B+-tree alike, are commonly employed as index structures; however, we found that the tree structure may not be appropriate for Non-Volatile Memory (NVM) in terms of the requirements for high-performance and high-endurance. This paper studies what is the best index structure for NVM-based systems and how to design such index structures. The design of an NVM-friendly index structure faces a lot of challenges. First, in order to prolong the lifetime of NVM, the write activities on NVM should be minimized. To this end, the index structure should be as simple as possible. The index proposed in this paper is based on the simplest data structure, i.e., linked list. Second, the simple structure brings challenges to achieve high-performance data retrieval operations. To overcome this challenge, we design a novel technique by explicitly building up a contiguous virtual address space on the linked list, such that efficient search algorithms can be performed. Third, we need to carefully consider data consistency issues in NVM-based systems, because the order of memory writes may be changed and the data content in NVM may be inconsistent due to write-back effects of CPU cache. This paper devises a novel indexing scheme, called 'Virtual Linear Addressable Buckets' (VLAB). We implement VLAB in a storage engine and plug it into MySQL. Evaluations are conducted on an NVDIMM workstation using YCSB workloads and real-world traces. Results show that write activities of the state-of-the-art indexes are 6.98 times more than ours; meanwhile, VLAB achieves 2.53 times speedup.
KW - NVM-based in-memory systems
KW - Non-volatile memory
KW - data consistency
KW - high performance
KW - indexing scheme
UR - https://www.scopus.com/pages/publications/85030631601
U2 - 10.1109/TC.2017.2754381
DO - 10.1109/TC.2017.2754381
M3 - 文章
AN - SCOPUS:85030631601
SN - 0018-9340
VL - 67
SP - 432
EP - 448
JO - IEEE Transactions on Computers
JF - IEEE Transactions on Computers
IS - 3
M1 - 8046077
ER -