Towards RTL test generation from SystemC TLM specifications

Mingsong Chen; Prabhat Mishra; Dhrubajyoti Kalita

doi:10.1109/HLDVT.2007.4392793

Towards RTL test generation from SystemC TLM specifications

Mingsong Chen^*
, Prabhat Mishra
, Dhrubajyoti Kalita

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

15 Scopus citations

Abstract

SystemC Transaction Level Modeling (TLM) is widely used to reduce the overall design and validation effort of complex System-on-Chip (SOC) architectures. Due to lack of efficient techniques, the amount of reuse between abstraction levels is limited in many scenarios such as reuse of TLM level tests for RTL validation. This paper presents a top-down methodology for generation of RTL tests from SystemC TLM specifications. This paper makes two important contributions: automatic test generation from TLM specification using a transition-based coverage metric and automatic translation of TLM tests into RTL tests using a set of transformation rules. Our initial results using a router design demonstrate the usefulness of our approach by capturing various functional errors as well as inconsistencies in the implementation.

Original language	English
Title of host publication	Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT
Pages	91-96
Number of pages	6
DOIs	https://doi.org/10.1109/HLDVT.2007.4392793
State	Published - 2007
Externally published	Yes
Event	IEEE International High-Level Design Validation and Test Workshop, HLDVT - Irvine, CA, United States Duration: 7 Nov 2007 → 9 Nov 2007

Publication series

Name	Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT
ISSN (Print)	1552-6674

Conference

Conference	IEEE International High-Level Design Validation and Test Workshop, HLDVT
Country/Territory	United States
City	Irvine, CA
Period	7/11/07 → 9/11/07

Access to Document

10.1109/HLDVT.2007.4392793

Cite this

@inproceedings{56a26d03bbf1436cabcd163becba5c8e,

title = "Towards RTL test generation from SystemC TLM specifications",

abstract = "SystemC Transaction Level Modeling (TLM) is widely used to reduce the overall design and validation effort of complex System-on-Chip (SOC) architectures. Due to lack of efficient techniques, the amount of reuse between abstraction levels is limited in many scenarios such as reuse of TLM level tests for RTL validation. This paper presents a top-down methodology for generation of RTL tests from SystemC TLM specifications. This paper makes two important contributions: automatic test generation from TLM specification using a transition-based coverage metric and automatic translation of TLM tests into RTL tests using a set of transformation rules. Our initial results using a router design demonstrate the usefulness of our approach by capturing various functional errors as well as inconsistencies in the implementation.",

author = "Mingsong Chen and Prabhat Mishra and Dhrubajyoti Kalita",

year = "2007",

doi = "10.1109/HLDVT.2007.4392793",

language = "英语",

isbn = "1424414806",

series = "Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT",

pages = "91--96",

booktitle = "Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT",

note = "IEEE International High-Level Design Validation and Test Workshop, HLDVT ; Conference date: 07-11-2007 Through 09-11-2007",

}

Chen, M, Mishra, P & Kalita, D 2007, Towards RTL test generation from SystemC TLM specifications. in Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT., 4392793, Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT, pp. 91-96, IEEE International High-Level Design Validation and Test Workshop, HLDVT, Irvine, CA, United States, 7/11/07. https://doi.org/10.1109/HLDVT.2007.4392793

Towards RTL test generation from SystemC TLM specifications. / Chen, Mingsong; Mishra, Prabhat; Kalita, Dhrubajyoti.
Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT. 2007. p. 91-96 4392793 (Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Towards RTL test generation from SystemC TLM specifications

AU - Chen, Mingsong

AU - Mishra, Prabhat

AU - Kalita, Dhrubajyoti

PY - 2007

Y1 - 2007

N2 - SystemC Transaction Level Modeling (TLM) is widely used to reduce the overall design and validation effort of complex System-on-Chip (SOC) architectures. Due to lack of efficient techniques, the amount of reuse between abstraction levels is limited in many scenarios such as reuse of TLM level tests for RTL validation. This paper presents a top-down methodology for generation of RTL tests from SystemC TLM specifications. This paper makes two important contributions: automatic test generation from TLM specification using a transition-based coverage metric and automatic translation of TLM tests into RTL tests using a set of transformation rules. Our initial results using a router design demonstrate the usefulness of our approach by capturing various functional errors as well as inconsistencies in the implementation.

AB - SystemC Transaction Level Modeling (TLM) is widely used to reduce the overall design and validation effort of complex System-on-Chip (SOC) architectures. Due to lack of efficient techniques, the amount of reuse between abstraction levels is limited in many scenarios such as reuse of TLM level tests for RTL validation. This paper presents a top-down methodology for generation of RTL tests from SystemC TLM specifications. This paper makes two important contributions: automatic test generation from TLM specification using a transition-based coverage metric and automatic translation of TLM tests into RTL tests using a set of transformation rules. Our initial results using a router design demonstrate the usefulness of our approach by capturing various functional errors as well as inconsistencies in the implementation.

UR - https://www.scopus.com/pages/publications/47949087135

U2 - 10.1109/HLDVT.2007.4392793

DO - 10.1109/HLDVT.2007.4392793

M3 - 会议稿件

AN - SCOPUS:47949087135

SN - 1424414806

SN - 9781424414802

T3 - Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT

SP - 91

EP - 96

BT - Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT

T2 - IEEE International High-Level Design Validation and Test Workshop, HLDVT

Y2 - 7 November 2007 through 9 November 2007

ER -

Towards RTL test generation from SystemC TLM specifications

Abstract

Publication series

Conference

Access to Document

Other files and links

Fingerprint

Cite this