Towards energy efficient hybrid on-chip scratch pad memory with non-volatile memory

Jingtong Hu; Chun Jason Xue; Qingfeng Zhuge; Wei Che Tseng; Edwin H.M. Sha

doi:10.1109/DATE.2011.5763127

Towards energy efficient hybrid on-chip scratch pad memory with non-volatile memory

Jingtong Hu^*
, Chun Jason Xue
, Qingfeng Zhuge
, Wei Che Tseng
, Edwin H.M. Sha

^*Corresponding author for this work

University of Texas at Dallas
City University of Hong Kong
Hunan University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

92 Scopus citations

Abstract

Scratch Pad Memory (SPM), a software-controlled on-chip memory, has been widely adopted in many embedded systems due to its small area and low power consumption. As technology scaling reaches the sub-micron level, leakage energy consumption is surpassing dynamic energy consumption and becoming a critical issue. In this paper, we propose a novel hybrid SPM which consists of non-volatile memory (NVM) and SRAM to take advantage of the ultra-low leakage power consumption and high density of NVM as well as the efficient writes of SRAM. A novel dynamic data allocation algorithm is proposed to make use of the full potential of both NVM and SRAM. According to the experimental results, with the help of the proposed algorithm, the novel hybrid SPM architecture can reduce memory access time by 18.17%, dynamic energy by 24.29%, and leakage power by 37.34% on average compared with a pure SRAM based SPM with the same size area.

Original language	English
Title of host publication	Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 2011
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	746-751
Number of pages	6
ISBN (Print)	9783981080179
DOIs	https://doi.org/10.1109/DATE.2011.5763127
State	Published - 2011
Externally published	Yes
Event	14th Design, Automation and Test in Europe, DATE 2011 - Grenoble, France Duration: 14 Apr 2014 → 18 Apr 2014

Publication series

Name	Proceedings -Design, Automation and Test in Europe, DATE
ISSN (Print)	1530-1591

Conference

Conference	14th Design, Automation and Test in Europe, DATE 2011
Country/Territory	France
City	Grenoble
Period	14/04/14 → 18/04/14

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

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10.1109/DATE.2011.5763127

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Hu, J., Xue, C. J., Zhuge, Q., Tseng, W. C., & Sha, E. H. M. (2011). Towards energy efficient hybrid on-chip scratch pad memory with non-volatile memory. In Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 2011 (pp. 746-751). Article 5763127 (Proceedings -Design, Automation and Test in Europe, DATE). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/DATE.2011.5763127

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title = "Towards energy efficient hybrid on-chip scratch pad memory with non-volatile memory",

abstract = "Scratch Pad Memory (SPM), a software-controlled on-chip memory, has been widely adopted in many embedded systems due to its small area and low power consumption. As technology scaling reaches the sub-micron level, leakage energy consumption is surpassing dynamic energy consumption and becoming a critical issue. In this paper, we propose a novel hybrid SPM which consists of non-volatile memory (NVM) and SRAM to take advantage of the ultra-low leakage power consumption and high density of NVM as well as the efficient writes of SRAM. A novel dynamic data allocation algorithm is proposed to make use of the full potential of both NVM and SRAM. According to the experimental results, with the help of the proposed algorithm, the novel hybrid SPM architecture can reduce memory access time by 18.17\%, dynamic energy by 24.29\%, and leakage power by 37.34\% on average compared with a pure SRAM based SPM with the same size area.",

author = "Jingtong Hu and Xue, \{Chun Jason\} and Qingfeng Zhuge and Tseng, \{Wei Che\} and Sha, \{Edwin H.M.\}",

year = "2011",

doi = "10.1109/DATE.2011.5763127",

language = "英语",

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series = "Proceedings -Design, Automation and Test in Europe, DATE",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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booktitle = "Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 2011",

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note = "14th Design, Automation and Test in Europe, DATE 2011 ; Conference date: 14-04-2014 Through 18-04-2014",

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Hu, J, Xue, CJ, Zhuge, Q, Tseng, WC & Sha, EHM 2011, Towards energy efficient hybrid on-chip scratch pad memory with non-volatile memory. in Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 2011., 5763127, Proceedings -Design, Automation and Test in Europe, DATE, Institute of Electrical and Electronics Engineers Inc., pp. 746-751, 14th Design, Automation and Test in Europe, DATE 2011, Grenoble, France, 14/04/14. https://doi.org/10.1109/DATE.2011.5763127

Towards energy efficient hybrid on-chip scratch pad memory with non-volatile memory. / Hu, Jingtong; Xue, Chun Jason; Zhuge, Qingfeng et al.
Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 2011. Institute of Electrical and Electronics Engineers Inc., 2011. p. 746-751 5763127 (Proceedings -Design, Automation and Test in Europe, DATE).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

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AU - Hu, Jingtong

AU - Xue, Chun Jason

AU - Zhuge, Qingfeng

AU - Tseng, Wei Che

AU - Sha, Edwin H.M.

PY - 2011

Y1 - 2011

N2 - Scratch Pad Memory (SPM), a software-controlled on-chip memory, has been widely adopted in many embedded systems due to its small area and low power consumption. As technology scaling reaches the sub-micron level, leakage energy consumption is surpassing dynamic energy consumption and becoming a critical issue. In this paper, we propose a novel hybrid SPM which consists of non-volatile memory (NVM) and SRAM to take advantage of the ultra-low leakage power consumption and high density of NVM as well as the efficient writes of SRAM. A novel dynamic data allocation algorithm is proposed to make use of the full potential of both NVM and SRAM. According to the experimental results, with the help of the proposed algorithm, the novel hybrid SPM architecture can reduce memory access time by 18.17%, dynamic energy by 24.29%, and leakage power by 37.34% on average compared with a pure SRAM based SPM with the same size area.

AB - Scratch Pad Memory (SPM), a software-controlled on-chip memory, has been widely adopted in many embedded systems due to its small area and low power consumption. As technology scaling reaches the sub-micron level, leakage energy consumption is surpassing dynamic energy consumption and becoming a critical issue. In this paper, we propose a novel hybrid SPM which consists of non-volatile memory (NVM) and SRAM to take advantage of the ultra-low leakage power consumption and high density of NVM as well as the efficient writes of SRAM. A novel dynamic data allocation algorithm is proposed to make use of the full potential of both NVM and SRAM. According to the experimental results, with the help of the proposed algorithm, the novel hybrid SPM architecture can reduce memory access time by 18.17%, dynamic energy by 24.29%, and leakage power by 37.34% on average compared with a pure SRAM based SPM with the same size area.

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Hu J, Xue CJ, Zhuge Q, Tseng WC, Sha EHM. Towards energy efficient hybrid on-chip scratch pad memory with non-volatile memory. In Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 2011. Institute of Electrical and Electronics Engineers Inc. 2011. p. 746-751. 5763127. (Proceedings -Design, Automation and Test in Europe, DATE). doi: 10.1109/DATE.2011.5763127

Towards energy efficient hybrid on-chip scratch pad memory with non-volatile memory

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