Thermal-aware rotation scheduling for 3D multi-core with timing constraint

Jiayin Li*, Meikang Qiu, Jingtong Hu, Edwin H.M. Sha

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

8 Scopus citations

Abstract

Multi-core technique has been implemented in DSP systems due to the tremendous computation requirements. In order to integrate more functionalities and provide higher performance, 3D multi-core architecture has been studied recently. The thermal issue is a critical problem for 3D architecture. In this paper, we propose an online thermal prediction model for 3D chip. Using this model, we present a task scheduling algorithm based on rotation scheduling to reduce the peak temperature on chip. While existing works do not consider the inter-iteration data dependencies in the application, we consider these dependencies in our proposed algorithm. Our simulation result shows that our algorithm can efficiently reduce the peak temperature up to 8°C.

Original languageEnglish
Title of host publication2010 IEEE Workshop on Signal Processing Systems, SiPS 2010 - Proceedings
Pages323-326
Number of pages4
DOIs
StatePublished - 2010
Externally publishedYes
Event2010 IEEE Workshop on Signal Processing Systems, SiPS 2010 - San Francisco, CA, United States
Duration: 6 Oct 20108 Oct 2010

Publication series

NameIEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
ISSN (Print)1520-6130

Conference

Conference2010 IEEE Workshop on Signal Processing Systems, SiPS 2010
Country/TerritoryUnited States
CitySan Francisco, CA
Period6/10/108/10/10

Keywords

  • DFG
  • DFVS
  • Peak temperature
  • Task scheduling
  • Thermal-aware
  • Timing constraint

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