Scheduling to optimize cache utilization for non-volatile main memories

Jingtong Hu; Qingfeng Zhuge; Chun Jason Xue; Wei Che Tseng; Shouzhen Gu; Edwin H.M. Sha

doi:10.1109/TC.2013.11

Scheduling to optimize cache utilization for non-volatile main memories

Jingtong Hu, Qingfeng Zhuge, Chun Jason Xue, Wei Che Tseng, Shouzhen Gu, Edwin H.M. Sha

Research output: Contribution to journal › Article › peer-review

11 Scopus citations

Abstract

In power and size sensitive embedded systems, non-volatile memories (NVMs) are replacing DRAM as the main memory since they have higher density, lower static power consumption, and lower costs. Unfortunately, these technologies are limited by their endurance and long write latencies. To minimize the main memory access time and extend the lifetime of the NVM, we optimally schedule tasks by an ILP formulation. We also present a heuristic, Concatenation Scheduling, to solve large problems in a reasonable amount of time. Our experimental results show that when compared with list scheduling, concatenation scheduling can reduce the total memory access time by an average of 9.99% and increase the lifetime of the NVM by 26.66%. When compared with list scheduling, ILP can reduce the total memory access time by an average of 12.39% and increase the lifetime of the NVM by 38.74%.

Original language	English
Article number	6409835
Pages (from-to)	2039-2051
Number of pages	13
Journal	IEEE Transactions on Computers
Volume	63
Issue number	8
DOIs	https://doi.org/10.1109/TC.2013.11
State	Published - Aug 2014
Externally published	Yes

Keywords

Cache memories
memory management
primary memory
real-time and embedded systems

Access to Document

10.1109/TC.2013.11

Cite this

@article{78dcd3b30fbe46319ff0007c6e60f615,

title = "Scheduling to optimize cache utilization for non-volatile main memories",

abstract = "In power and size sensitive embedded systems, non-volatile memories (NVMs) are replacing DRAM as the main memory since they have higher density, lower static power consumption, and lower costs. Unfortunately, these technologies are limited by their endurance and long write latencies. To minimize the main memory access time and extend the lifetime of the NVM, we optimally schedule tasks by an ILP formulation. We also present a heuristic, Concatenation Scheduling, to solve large problems in a reasonable amount of time. Our experimental results show that when compared with list scheduling, concatenation scheduling can reduce the total memory access time by an average of 9.99\% and increase the lifetime of the NVM by 26.66\%. When compared with list scheduling, ILP can reduce the total memory access time by an average of 12.39\% and increase the lifetime of the NVM by 38.74\%.",

keywords = "Cache memories, memory management, primary memory, real-time and embedded systems",

author = "Jingtong Hu and Qingfeng Zhuge and Xue, \{Chun Jason\} and Tseng, \{Wei Che\} and Shouzhen Gu and Sha, \{Edwin H.M.\}",

year = "2014",

month = aug,

doi = "10.1109/TC.2013.11",

language = "英语",

volume = "63",

pages = "2039--2051",

journal = "IEEE Transactions on Computers",

issn = "0018-9340",

publisher = "IEEE Computer Society",

number = "8",

}

TY - JOUR

T1 - Scheduling to optimize cache utilization for non-volatile main memories

AU - Hu, Jingtong

AU - Zhuge, Qingfeng

AU - Xue, Chun Jason

AU - Tseng, Wei Che

AU - Gu, Shouzhen

AU - Sha, Edwin H.M.

PY - 2014/8

Y1 - 2014/8

N2 - In power and size sensitive embedded systems, non-volatile memories (NVMs) are replacing DRAM as the main memory since they have higher density, lower static power consumption, and lower costs. Unfortunately, these technologies are limited by their endurance and long write latencies. To minimize the main memory access time and extend the lifetime of the NVM, we optimally schedule tasks by an ILP formulation. We also present a heuristic, Concatenation Scheduling, to solve large problems in a reasonable amount of time. Our experimental results show that when compared with list scheduling, concatenation scheduling can reduce the total memory access time by an average of 9.99% and increase the lifetime of the NVM by 26.66%. When compared with list scheduling, ILP can reduce the total memory access time by an average of 12.39% and increase the lifetime of the NVM by 38.74%.

AB - In power and size sensitive embedded systems, non-volatile memories (NVMs) are replacing DRAM as the main memory since they have higher density, lower static power consumption, and lower costs. Unfortunately, these technologies are limited by their endurance and long write latencies. To minimize the main memory access time and extend the lifetime of the NVM, we optimally schedule tasks by an ILP formulation. We also present a heuristic, Concatenation Scheduling, to solve large problems in a reasonable amount of time. Our experimental results show that when compared with list scheduling, concatenation scheduling can reduce the total memory access time by an average of 9.99% and increase the lifetime of the NVM by 26.66%. When compared with list scheduling, ILP can reduce the total memory access time by an average of 12.39% and increase the lifetime of the NVM by 38.74%.

KW - Cache memories

KW - memory management

KW - primary memory

KW - real-time and embedded systems

UR - https://www.scopus.com/pages/publications/84904786486

U2 - 10.1109/TC.2013.11

DO - 10.1109/TC.2013.11

M3 - 文章

AN - SCOPUS:84904786486

SN - 0018-9340

VL - 63

SP - 2039

EP - 2051

JO - IEEE Transactions on Computers

JF - IEEE Transactions on Computers

IS - 8

M1 - 6409835

ER -

Scheduling to optimize cache utilization for non-volatile main memories

Abstract

Keywords

Access to Document

Other files and links

Fingerprint

Cite this