SCEval: An Open-Source Platform for Standardized Evaluation and Optimization of Standard Cell Libraries in Next-Generation Process Nodes

With the introduction of new process technology, the cost of developing standard cell libraries has escalated due to the need for multiple design iterations to optimize performance within given constraints. This challenge is compounded by the growing number of standard cells and process corners, and is further exacerbated by error-prone, manually-created netlists and test benches. In this work, we introduce the SCEval platform, where users can submit SPICE netlist files and receive corresponding evaluation results and charts post-simulation. Users can leverage our standardized SCEval platform to assess and enhance their standard cell circuits, which is integral to the DTCO process. Additionally, students new to standard cell circuit design can learn how to conduct standardized evaluations of standard cells through our platform.