RRAM Mirrored and RRAM-Transistor Hybrid Single Device Logic Gates Based on Two-Dimensional Materials

The unsustainable downscaling of Si transistor run counter to the rapid development of big data. Further geometric sizing needs industrial strategies and promotion. The two-dimensional materials emerge as excellent choice, allowing potential realization of area-efficient electronic circuit. Moreover, some novel architectures different from CMOS technology have also been reported. Based on that, we propose RRAM mirrored and RRAM-transistor hybrid single transistor logic gates that can realize non-volatile and switchable function. The internal equivalent circuits and corresponding operation scheme have been analyzed and illustrated. SPICE simulations have also been conducted to theoretically validate the feasibility of the devices. The benchmarked area reduction in standard cell can reach to 33% compared to conventional CMOS circuits, which show great protentional to enable next generation electronics. Moreover, the non-volatile devices proposed in this work can enable the logic-in-memory calculation for the next generation calculations.