Research on computing IP core for the digital signature algorithm

Jianpeng Chu; Yongsheng Xu; Xiaojin Li; Zongsheng Lai

doi:10.1109/ICASIC.2003.1277462

Research on computing IP core for the digital signature algorithm

Jianpeng Chu
, Yongsheng Xu
, Xiaojin Li
, Zongsheng Lai^*

^*Corresponding author for this work

School of Communication and Electronic Engineering

East China Normal University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

Polynomial multiplication with big integer coefficients over finite field is frequently used in some digital signature algorithms, in which this kind of calculation is the most time consuming part realized by software. This paper presents a new method (FFT/IFFT) and try to solve it using FPGA. With the reduced calculation amount compared with normal algorithm and realized in hardware, it will greatly raise not only the performance of this calculation procedure but also the level of security. At the end of this paper, some intermediate results are given.

Original language	English
Title of host publication	ASICON 2003 - 2003 5th International Conference on ASIC, Proceedings
Editors	Ting-Ao Tang, Wenhong Li, Huihua Yu
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	1329-1331
Number of pages	3
ISBN (Electronic)	078037889X
DOIs	https://doi.org/10.1109/ICASIC.2003.1277462
State	Published - 2003
Event	5th International Conference on ASIC, ASICON 2003 - Beijing, China Duration: 21 Oct 2003 → 24 Oct 2003

Publication series

Name	IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings
Volume	2
ISSN (Print)	1523-553X

Conference

Conference	5th International Conference on ASIC, ASICON 2003
Country/Territory	China
City	Beijing
Period	21/10/03 → 24/10/03

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10.1109/ICASIC.2003.1277462

Cite this

Chu, J., Xu, Y., Li, X., & Lai, Z. (2003). Research on computing IP core for the digital signature algorithm. In T.-A. Tang, W. Li, & H. Yu (Eds.), ASICON 2003 - 2003 5th International Conference on ASIC, Proceedings (pp. 1329-1331). Article 5733649 (IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings; Vol. 2). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICASIC.2003.1277462

Chu, Jianpeng ; Xu, Yongsheng ; Li, Xiaojin et al. / Research on computing IP core for the digital signature algorithm. ASICON 2003 - 2003 5th International Conference on ASIC, Proceedings. editor / Ting-Ao Tang ; Wenhong Li ; Huihua Yu. Institute of Electrical and Electronics Engineers Inc., 2003. pp. 1329-1331 (IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings).

@inproceedings{474a7df7ce944d83aeec5d0ec66457e9,

title = "Research on computing IP core for the digital signature algorithm",

abstract = "Polynomial multiplication with big integer coefficients over finite field is frequently used in some digital signature algorithms, in which this kind of calculation is the most time consuming part realized by software. This paper presents a new method (FFT/IFFT) and try to solve it using FPGA. With the reduced calculation amount compared with normal algorithm and realized in hardware, it will greatly raise not only the performance of this calculation procedure but also the level of security. At the end of this paper, some intermediate results are given.",

author = "Jianpeng Chu and Yongsheng Xu and Xiaojin Li and Zongsheng Lai",

note = "Publisher Copyright: {\textcopyright} 2003 IEEE; 5th International Conference on ASIC, ASICON 2003 ; Conference date: 21-10-2003 Through 24-10-2003",

year = "2003",

doi = "10.1109/ICASIC.2003.1277462",

language = "英语",

series = "IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "1329--1331",

editor = "Ting-Ao Tang and Wenhong Li and Huihua Yu",

booktitle = "ASICON 2003 - 2003 5th International Conference on ASIC, Proceedings",

address = "美国",

}

Chu, J, Xu, Y, Li, X & Lai, Z 2003, Research on computing IP core for the digital signature algorithm. in T-A Tang, W Li & H Yu (eds), ASICON 2003 - 2003 5th International Conference on ASIC, Proceedings., 5733649, IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings, vol. 2, Institute of Electrical and Electronics Engineers Inc., pp. 1329-1331, 5th International Conference on ASIC, ASICON 2003, Beijing, China, 21/10/03. https://doi.org/10.1109/ICASIC.2003.1277462

Research on computing IP core for the digital signature algorithm. / Chu, Jianpeng; Xu, Yongsheng; Li, Xiaojin et al.
ASICON 2003 - 2003 5th International Conference on ASIC, Proceedings. ed. / Ting-Ao Tang; Wenhong Li; Huihua Yu. Institute of Electrical and Electronics Engineers Inc., 2003. p. 1329-1331 5733649 (IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings; Vol. 2).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Research on computing IP core for the digital signature algorithm

AU - Chu, Jianpeng

AU - Xu, Yongsheng

AU - Li, Xiaojin

AU - Lai, Zongsheng

PY - 2003

Y1 - 2003

N2 - Polynomial multiplication with big integer coefficients over finite field is frequently used in some digital signature algorithms, in which this kind of calculation is the most time consuming part realized by software. This paper presents a new method (FFT/IFFT) and try to solve it using FPGA. With the reduced calculation amount compared with normal algorithm and realized in hardware, it will greatly raise not only the performance of this calculation procedure but also the level of security. At the end of this paper, some intermediate results are given.

AB - Polynomial multiplication with big integer coefficients over finite field is frequently used in some digital signature algorithms, in which this kind of calculation is the most time consuming part realized by software. This paper presents a new method (FFT/IFFT) and try to solve it using FPGA. With the reduced calculation amount compared with normal algorithm and realized in hardware, it will greatly raise not only the performance of this calculation procedure but also the level of security. At the end of this paper, some intermediate results are given.

UR - https://www.scopus.com/pages/publications/85085518241

U2 - 10.1109/ICASIC.2003.1277462

DO - 10.1109/ICASIC.2003.1277462

M3 - 会议稿件

AN - SCOPUS:85085518241

T3 - IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings

SP - 1329

EP - 1331

BT - ASICON 2003 - 2003 5th International Conference on ASIC, Proceedings

A2 - Tang, Ting-Ao

A2 - Li, Wenhong

A2 - Yu, Huihua

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 5th International Conference on ASIC, ASICON 2003

Y2 - 21 October 2003 through 24 October 2003

ER -

Chu J, Xu Y, Li X, Lai Z. Research on computing IP core for the digital signature algorithm. In Tang TA, Li W, Yu H, editors, ASICON 2003 - 2003 5th International Conference on ASIC, Proceedings. Institute of Electrical and Electronics Engineers Inc. 2003. p. 1329-1331. 5733649. (IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings). doi: 10.1109/ICASIC.2003.1277462

Research on computing IP core for the digital signature algorithm

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