Relaxed Placement: Minimizing Shift Operations for Racetrack Memory in Hybrid SPM

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

5 Scopus citations

Abstract

Racetrack memory (RM) has high access performance comparable to SRAM. It is a kind of non-volatile memory (NVM), which consists of data block clusters (DBCs) and access ports. However, data accessing on RM is based on shift operations, which will decrease the performance of RM. This paper proposes techniques by using SRAM to reduce the shifts and improve the accessing performance of RM. The key idea is to place randomly accessed data on SRAM ahead of time to relax the data placement on RM. First, a greedy scheduling strategy is proposed to reduce the requirement of SRAM. Second, to further reduce shifts, data with similar association degree are grouped and allocated to each DBC. Experimental results show that the proposed techniques reduce the shifts by 72.3% with only 256-byte SRAM compared to pure RM.

Original languageEnglish
Title of host publicationGLSVLSI 2021 - Proceedings of the 2021 Great Lakes Symposium on VLSI
PublisherAssociation for Computing Machinery
Pages129-134
Number of pages6
ISBN (Electronic)9781450383936
DOIs
StatePublished - 22 Jun 2021
Event31st Great Lakes Symposium on VLSI, GLSVLSI 2021 - Virtual, Online, United States
Duration: 22 Jun 202125 Jun 2021

Publication series

NameProceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Conference

Conference31st Great Lakes Symposium on VLSI, GLSVLSI 2021
Country/TerritoryUnited States
CityVirtual, Online
Period22/06/2125/06/21

Keywords

  • data placement
  • hybrid spm
  • racetrack memory
  • shift operation

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