Register-constrained inclusion scheduling for imprecise specification

C. Chantrapornchai; W. Surakumpolthorn; E. H.M. Sha

Register-constrained inclusion scheduling for imprecise specification

C. Chantrapornchai^*
, W. Surakumpolthorn
, E. H.M. Sha

^*Corresponding author for this work

Research output: Contribution to conference › Paper › peer-review

Abstract

This paper proposes a scheduling algorithm which considers imprecise system characteristics and constraints. We create a model to model the imprecise latency characteristic as well as imprecsie register usage based on fuzzy sets. Given a set of functional units, the proposed algorithm attempts to create a schedule which minimizes the latency and register usage, maximizing overall satisfiability. The experiments show that we can achieve an acceptable schedule with upto 30% saving of number of registers compared to the original algorithm.

Original language	English
Pages	B160-B163
State	Published - 2004
Externally published	Yes
Event	IEEE TENCON 2004 - 2004 IEEE Region 10 Conference: Analog and Digital Techniques in Electrical Engineering - Chiang Mai, Thailand Duration: 21 Nov 2004 → 24 Nov 2004

Conference

Conference	IEEE TENCON 2004 - 2004 IEEE Region 10 Conference: Analog and Digital Techniques in Electrical Engineering
Country/Territory	Thailand
City	Chiang Mai
Period	21/11/04 → 24/11/04

Keywords

Imprecise information
Inclusion Scheduling
Multiple design attributes
Register constraint
Scheduling/Allocation

Cite this

@conference{5a3233dade64445fa959062295f33096,

title = "Register-constrained inclusion scheduling for imprecise specification",

abstract = "This paper proposes a scheduling algorithm which considers imprecise system characteristics and constraints. We create a model to model the imprecise latency characteristic as well as imprecsie register usage based on fuzzy sets. Given a set of functional units, the proposed algorithm attempts to create a schedule which minimizes the latency and register usage, maximizing overall satisfiability. The experiments show that we can achieve an acceptable schedule with upto 30\% saving of number of registers compared to the original algorithm.",

keywords = "Imprecise information, Inclusion Scheduling, Multiple design attributes, Register constraint, Scheduling/Allocation",

author = "C. Chantrapornchai and W. Surakumpolthorn and Sha, \{E. H.M.\}",

year = "2004",

language = "英语",

pages = "B160--B163",

note = "IEEE TENCON 2004 - 2004 IEEE Region 10 Conference: Analog and Digital Techniques in Electrical Engineering ; Conference date: 21-11-2004 Through 24-11-2004",

}

TY - CONF

T1 - Register-constrained inclusion scheduling for imprecise specification

AU - Chantrapornchai, C.

AU - Surakumpolthorn, W.

AU - Sha, E. H.M.

PY - 2004

Y1 - 2004

N2 - This paper proposes a scheduling algorithm which considers imprecise system characteristics and constraints. We create a model to model the imprecise latency characteristic as well as imprecsie register usage based on fuzzy sets. Given a set of functional units, the proposed algorithm attempts to create a schedule which minimizes the latency and register usage, maximizing overall satisfiability. The experiments show that we can achieve an acceptable schedule with upto 30% saving of number of registers compared to the original algorithm.

AB - This paper proposes a scheduling algorithm which considers imprecise system characteristics and constraints. We create a model to model the imprecise latency characteristic as well as imprecsie register usage based on fuzzy sets. Given a set of functional units, the proposed algorithm attempts to create a schedule which minimizes the latency and register usage, maximizing overall satisfiability. The experiments show that we can achieve an acceptable schedule with upto 30% saving of number of registers compared to the original algorithm.

KW - Imprecise information

KW - Inclusion Scheduling

KW - Multiple design attributes

KW - Register constraint

KW - Scheduling/Allocation

UR - https://www.scopus.com/pages/publications/27944436643

M3 - 论文

AN - SCOPUS:27944436643

SP - B160-B163

T2 - IEEE TENCON 2004 - 2004 IEEE Region 10 Conference: Analog and Digital Techniques in Electrical Engineering

Y2 - 21 November 2004 through 24 November 2004

ER -

Register-constrained inclusion scheduling for imprecise specification

Abstract

Conference

Keywords

Other files and links

Fingerprint

Cite this