@inproceedings{be1bc58abadb47c683b9ec0a2cfd3605,
title = "RC Tightened Corner Test structure Design and Silicon Characterization in FinFET Technology",
abstract = "In this work, we propose a novel RC tightened corner test structure for FinFET Technology. In this test structure, Parasitic RC DUTs (Design Under Test) integrated into RO (Ring Oscillator) have been designed to verify and calibrate MEOL (Mid-End-Of-Line) and BEOL (Back-End-Of-Line) RC tightened corner; On the other hands, addressable-Array circuit has been used to avoid noise induced by the local variation of FEOL (Front-End-Of-Line) transistors. By the test structure silicon data, RC tightened corners generated from statistical simulation have been iterated and updated.",
author = "Lijie Sun and Mengying Zhang and Guangxing Wan and Waisum Wong and Zhen Zhou and Xiaojin Li and Yabin Sun and Yanling Shi",
note = "Publisher Copyright: {\textcopyright} 2020 IEEE.; 15th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2020 ; Conference date: 03-11-2020 Through 06-11-2020",
year = "2020",
month = nov,
day = "3",
doi = "10.1109/ICSICT49897.2020.9278392",
language = "英语",
series = "2020 IEEE 15th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2020 - Proceedings",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
editor = "Shaofeng Yu and Xiaona Zhu and Ting-Ao Tang",
booktitle = "2020 IEEE 15th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2020 - Proceedings",
address = "美国",
}