Physics-based analysis and simulation model of electromagnetic interference induced soft logic upset in CMOS inverter

The instantaneous reversible soft logic upset induced by the electromagnetic interference (EMI) severely affects the performances and reliabilities of complementary metal-oxide-semiconductor (CMOS) inverters. This kind of soft logic upset is investigated in theory and simulation. Physics-based analysis is performed, and the result shows that the upset is caused by the non-equilibrium carrier accumulation in channels, which can ultimately lead to an abnormal turn-on of specific metal-oxide-semiconductor field-effect transistor (MOSFET) in CMOS inverter. Then a soft logic upset simulation model is introduced. Using this model, analysis of upset characteristic reveals an increasing susceptibility under higher injection powers, which accords well with experimental results, and the influences of EMI frequency and device size are studied respectively using the same model. The research indicates that in a range from L waveband to C waveband, lower interference frequency and smaller device size are more likely to be affected by the soft logic upset.