Performance Trade-offs in Complementary FET (CFET) Device Architectures for 3nm-node and beyond

Xiaoqiao Yang; Yabin Sun; Ziyu Liu; Yanling Shi; Xiaojin Li

doi:10.1109/EDTM50988.2021.9420820

Performance Trade-offs in Complementary FET (CFET) Device Architectures for 3nm-node and beyond

Xiaoqiao Yang
, Yabin Sun^*
, Ziyu Liu^*
, Yanling Shi
, Xiaojin Li

^*Corresponding author for this work

School of Communication and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

7 Scopus citations

Abstract

A comparative analysis of DC/AC performance of complementary FET (CFET) is presented by 3D TCAD simulation for 3nm-node and beyond. Three types of device architectures with different structure parameters are investigated and compared on some critical electrical characteristics. Through adjusting the fin height and width, the source/drain-extension-to-gate underlap length and the n-/p-FET separator thickness and material, the tradeoff between DC and AC performance is shown to give an optimized CFET device architecture.

Original language	English
Title of host publication	2021 5th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2021
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728181769
DOIs	https://doi.org/10.1109/EDTM50988.2021.9420820
State	Published - 8 Apr 2021
Event	5th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2021 - Chengdu, China Duration: 8 Apr 2021 → 11 Apr 2021

Publication series

Name	2021 5th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2021

Conference

Conference	5th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2021
Country/Territory	China
City	Chengdu
Period	8/04/21 → 11/04/21

Keywords

CFET
TCAD
gate-all-around (GAA)

Access to Document

10.1109/EDTM50988.2021.9420820

Cite this

Yang, X., Sun, Y., Liu, Z., Shi, Y., & Li, X. (2021). Performance Trade-offs in Complementary FET (CFET) Device Architectures for 3nm-node and beyond. In 2021 5th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2021 Article 9420820 (2021 5th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2021). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/EDTM50988.2021.9420820

Yang, Xiaoqiao ; Sun, Yabin ; Liu, Ziyu et al. / Performance Trade-offs in Complementary FET (CFET) Device Architectures for 3nm-node and beyond. 2021 5th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2021. Institute of Electrical and Electronics Engineers Inc., 2021. (2021 5th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2021).

@inproceedings{7ccca13e88a142be96de83b9cf0d0a4a,

title = "Performance Trade-offs in Complementary FET (CFET) Device Architectures for 3nm-node and beyond",

abstract = "A comparative analysis of DC/AC performance of complementary FET (CFET) is presented by 3D TCAD simulation for 3nm-node and beyond. Three types of device architectures with different structure parameters are investigated and compared on some critical electrical characteristics. Through adjusting the fin height and width, the source/drain-extension-to-gate underlap length and the n-/p-FET separator thickness and material, the tradeoff between DC and AC performance is shown to give an optimized CFET device architecture.",

keywords = "CFET, TCAD, gate-all-around (GAA)",

author = "Xiaoqiao Yang and Yabin Sun and Ziyu Liu and Yanling Shi and Xiaojin Li",

note = "Publisher Copyright: {\textcopyright} 2021 IEEE.; 5th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2021 ; Conference date: 08-04-2021 Through 11-04-2021",

year = "2021",

month = apr,

day = "8",

doi = "10.1109/EDTM50988.2021.9420820",

language = "英语",

series = "2021 5th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2021",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2021 5th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2021",

address = "美国",

}

Yang, X, Sun, Y, Liu, Z, Shi, Y & Li, X 2021, Performance Trade-offs in Complementary FET (CFET) Device Architectures for 3nm-node and beyond. in 2021 5th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2021., 9420820, 2021 5th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2021, Institute of Electrical and Electronics Engineers Inc., 5th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2021, Chengdu, China, 8/04/21. https://doi.org/10.1109/EDTM50988.2021.9420820

Performance Trade-offs in Complementary FET (CFET) Device Architectures for 3nm-node and beyond. / Yang, Xiaoqiao; Sun, Yabin; Liu, Ziyu et al.
2021 5th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2021. Institute of Electrical and Electronics Engineers Inc., 2021. 9420820 (2021 5th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2021).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Performance Trade-offs in Complementary FET (CFET) Device Architectures for 3nm-node and beyond

AU - Yang, Xiaoqiao

AU - Sun, Yabin

AU - Liu, Ziyu

AU - Shi, Yanling

AU - Li, Xiaojin

PY - 2021/4/8

Y1 - 2021/4/8

N2 - A comparative analysis of DC/AC performance of complementary FET (CFET) is presented by 3D TCAD simulation for 3nm-node and beyond. Three types of device architectures with different structure parameters are investigated and compared on some critical electrical characteristics. Through adjusting the fin height and width, the source/drain-extension-to-gate underlap length and the n-/p-FET separator thickness and material, the tradeoff between DC and AC performance is shown to give an optimized CFET device architecture.

AB - A comparative analysis of DC/AC performance of complementary FET (CFET) is presented by 3D TCAD simulation for 3nm-node and beyond. Three types of device architectures with different structure parameters are investigated and compared on some critical electrical characteristics. Through adjusting the fin height and width, the source/drain-extension-to-gate underlap length and the n-/p-FET separator thickness and material, the tradeoff between DC and AC performance is shown to give an optimized CFET device architecture.

KW - CFET

KW - TCAD

KW - gate-all-around (GAA)

UR - https://www.scopus.com/pages/publications/85106489262

U2 - 10.1109/EDTM50988.2021.9420820

DO - 10.1109/EDTM50988.2021.9420820

M3 - 会议稿件

AN - SCOPUS:85106489262

T3 - 2021 5th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2021

BT - 2021 5th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2021

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 5th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2021

Y2 - 8 April 2021 through 11 April 2021

ER -

Yang X, Sun Y, Liu Z, Shi Y, Li X. Performance Trade-offs in Complementary FET (CFET) Device Architectures for 3nm-node and beyond. In 2021 5th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2021. Institute of Electrical and Electronics Engineers Inc. 2021. 9420820. (2021 5th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2021). doi: 10.1109/EDTM50988.2021.9420820

Performance Trade-offs in Complementary FET (CFET) Device Architectures for 3nm-node and beyond

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