TY - GEN
T1 - Parallel Implementation of H.265 Intra-Frame Coding Based on FPGA Heterogeneous Platform
AU - Chen, Wenjie
AU - He, Qunfang
AU - Li, Shen
AU - Xiao, Bo
AU - Chen, Mingsong
AU - Chai, Zhilei
N1 - Publisher Copyright:
© 2020 IEEE.
PY - 2020/12
Y1 - 2020/12
N2 - The new video coding algorithm H.265 achieved twice compression rate than the prevailing H.264, but the encoding speed is reduced several times, making it difficult for the real-Time applications such as video surveillance and remote meeting. In this paper, we design a parallel intra-frame mode decision architecture based on FPGA to accelerate the coding. We prove that the mode decision problem of multi-level large coding unit of H.265 can be transformed into the accumulation of multiple single-level small coding unit mode decision. Furthermore, we design how mode decision is accelerated by fine-grained parallelism within coding unit, and pipelining among coding units, then implement them on FPGA. The experimental results show that the proposed architecture achieves maximum 93.6\times acceleration compare with the ARM A53 platform, with an insignificant loss of video quality.
AB - The new video coding algorithm H.265 achieved twice compression rate than the prevailing H.264, but the encoding speed is reduced several times, making it difficult for the real-Time applications such as video surveillance and remote meeting. In this paper, we design a parallel intra-frame mode decision architecture based on FPGA to accelerate the coding. We prove that the mode decision problem of multi-level large coding unit of H.265 can be transformed into the accumulation of multiple single-level small coding unit mode decision. Furthermore, we design how mode decision is accelerated by fine-grained parallelism within coding unit, and pipelining among coding units, then implement them on FPGA. The experimental results show that the proposed architecture achieves maximum 93.6\times acceleration compare with the ARM A53 platform, with an insignificant loss of video quality.
KW - FPGA heterogeneous platform
KW - H.265
KW - HEVC
KW - hardware acceleration
KW - intra-frame coding
KW - mode decision
UR - https://www.scopus.com/pages/publications/85105337006
U2 - 10.1109/HPCC-SmartCity-DSS50907.2020.00096
DO - 10.1109/HPCC-SmartCity-DSS50907.2020.00096
M3 - 会议稿件
AN - SCOPUS:85105337006
T3 - Proceedings - 2020 IEEE 22nd International Conference on High Performance Computing and Communications, IEEE 18th International Conference on Smart City and IEEE 6th International Conference on Data Science and Systems, HPCC-SmartCity-DSS 2020
SP - 736
EP - 743
BT - Proceedings - 2020 IEEE 22nd International Conference on High Performance Computing and Communications, IEEE 18th International Conference on Smart City and IEEE 6th International Conference on Data Science and Systems, HPCC-SmartCity-DSS 2020
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 22nd IEEE International Conference on High Performance Computing and Communications, 18th IEEE International Conference on Smart City and 6th IEEE International Conference on Data Science and Systems, HPCC-SmartCity-DSS 2020
Y2 - 14 December 2020 through 16 December 2020
ER -