TY - GEN
T1 - Parallel HD encoding on cell
AU - Xun, He
AU - Xiangzhong, Fang
AU - Ci, Wang
AU - Satoshi, Goto
PY - 2009
Y1 - 2009
N2 - The Cell Broadband Engine Architecture (CBEA) is an excellent architecture for high performance distributed computing and multimedia processing. While the Cell/BE processor is capable of high definition H.264 encoding, there are still no such implementations available. In this paper, we present a parallel implementation of a HD H.264 encoder on this heterogeneous nine cores processor. First we implement a real time SD encoder on a single SPU by optimizing Motion Estimation algorithm, DMA transfers etc. Then we propose a pipelined parallel encoding algorithm for multicore processors, and use this algorithm to get a real time HD H.264 encoder (1920x1080@31fps) by using eight SPEs (58fps on 16 SPEs).
AB - The Cell Broadband Engine Architecture (CBEA) is an excellent architecture for high performance distributed computing and multimedia processing. While the Cell/BE processor is capable of high definition H.264 encoding, there are still no such implementations available. In this paper, we present a parallel implementation of a HD H.264 encoder on this heterogeneous nine cores processor. First we implement a real time SD encoder on a single SPU by optimizing Motion Estimation algorithm, DMA transfers etc. Then we propose a pipelined parallel encoding algorithm for multicore processors, and use this algorithm to get a real time HD H.264 encoder (1920x1080@31fps) by using eight SPEs (58fps on 16 SPEs).
UR - https://www.scopus.com/pages/publications/70350138503
U2 - 10.1109/ISCAS.2009.5117943
DO - 10.1109/ISCAS.2009.5117943
M3 - 会议稿件
AN - SCOPUS:70350138503
SN - 9781424438280
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 1065
EP - 1068
BT - 2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009
T2 - 2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009
Y2 - 24 May 2009 through 27 May 2009
ER -