Parallel embedded systems: Optimizations and challenges

With the advance of system level integration and system-on-chip, the high-tech industry is now moving toward multiple-core parallel embedded systems using hardware/software co-design approach. To design and optimize an embedded system and its software is technically hard because of the strict requirements of an embedded system in timing, code size, memory, low power, security, etc. while optimizing a parallel embedded system makes research even more challenging. We will focus on loops because they are usually the most critical parts to be optimized in DSP or any computation-intensive applications. Because of the space limit, this paper will only show the basic ideas of fully parallelizing nested loops while minimizing code size overhead. Using our technique based on multidimensional retiming, any uniform nested loops can be transformed with minimal overhead such that all the computations in the new loop body can be executed simultaneously. This is the best possible result and can be applied to many applications executed on VLIW or other types of parallel systems.