Parallel all the time: Plane Level Parallelism Exploration for High Performance SSDs

  • Congming Gao
  • , Liang Shi
  • , Chun Jason Xue
  • , Cheng Ji
  • , Jun Yang
  • , Youtao Zhang

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

31 Scopus citations

Abstract

Solid state drives (SSDs) are constructed with multiple level parallel organization, including channels, chips, dies and planes. Among these parallel levels, plane level parallelism, which is the last level parallelism of SSDs, has the most strict restrictions. Only the same type of operations which access the same address in different planes can be processed in parallel. In order to maximize the access performance, several previous works have been proposed to exploit the plane level parallelism for host accesses and internal operations of SSDs. However, our preliminary studies show that the plane level parallelism is far from well utilized and should be further improved. The reason is that the strict restrictions of plane level parallelism are hard to be satisfied. In this work, a from plane to die parallel optimization framework is proposed to exploit the plane level parallelism through smartly satisfying the strict restrictions all the time. In order to achieve the objective, there are at least two challenges. First, due to that host access patterns are always complex, receiving multiple same-type requests to different planes at the same time is uncommon. Second, there are many internal activities, such as garbage collection (GC), which may destroy the restrictions. In order to solve above challenges, two schemes are proposed in the SSD controller: First, a die level write construction scheme is designed to make sure there are always N pages of data written by each write operation. Second, in a further step, a die level GC scheme is proposed to activate GC in the unit of all planes in the same die. Combing the die level write and die level GC, write accesses from both host write operations and GC induced valid page movements can be processed in parallel at all time. As a result, the GC cost and average write latency can be significantly reduced. Experiment results show that the proposed framework is able to significantly improve the write performance without read performance impact.

Original languageEnglish
Title of host publicationProceedings - 2019 35th Symposium on Mass Storage Systems and Technologies, MSST 2019
PublisherIEEE Computer Society
Pages172-184
Number of pages13
ISBN (Electronic)9781728139203
DOIs
StatePublished - May 2019
Event35th Symposium on Mass Storage Systems and Technologies, MSST 2019 - Santa Clara, United States
Duration: 20 May 201924 May 2019

Publication series

NameIEEE Symposium on Mass Storage Systems and Technologies
Volume2019-May
ISSN (Print)2160-1968

Conference

Conference35th Symposium on Mass Storage Systems and Technologies, MSST 2019
Country/TerritoryUnited States
CitySanta Clara
Period20/05/1924/05/19

Keywords

  • Parallelism
  • Performance Improvement
  • SSD
  • Storage

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