TY - GEN
T1 - Optimizing data placement for reducing shift operations on Domain Wall Memories
AU - Chen, Xianzhang
AU - Sha, Edwin H.M.
AU - Zhuge, Qingfeng
AU - Dai, Penglin
AU - Jiang, Weiwen
N1 - Publisher Copyright:
© 2015 ACM.
PY - 2015/7/24
Y1 - 2015/7/24
N2 - Domain Wall Memory (DWM) using nanowire with data access port, exhibits extraordinary high density, low power leakage, and low access latency. These properties enable DWM to become an attractive candidate for replacing traditional memories. However, data accesses on DWM may require multIPle shift operations before the port points to requested data, resulting in varying access latencies. Data placement, therefore, has a significant impact on the performance of data accesses on DWM. This paper studies compiler-based optimization techniques for data placement on DWM. To the authors' best knowledge, this is the first work addressing data placement problem on DWM. We present an efficient heuristic, called Grouping-Based Data Placement (GBDP), for the data placement problem of a given data access sequence on DWM. The experimental results show that GBDP has a significant performance improvement; for example, GBDP reduces 82% shift operations on an 8-port DWM compared with non-optimized approach.
AB - Domain Wall Memory (DWM) using nanowire with data access port, exhibits extraordinary high density, low power leakage, and low access latency. These properties enable DWM to become an attractive candidate for replacing traditional memories. However, data accesses on DWM may require multIPle shift operations before the port points to requested data, resulting in varying access latencies. Data placement, therefore, has a significant impact on the performance of data accesses on DWM. This paper studies compiler-based optimization techniques for data placement on DWM. To the authors' best knowledge, this is the first work addressing data placement problem on DWM. We present an efficient heuristic, called Grouping-Based Data Placement (GBDP), for the data placement problem of a given data access sequence on DWM. The experimental results show that GBDP has a significant performance improvement; for example, GBDP reduces 82% shift operations on an 8-port DWM compared with non-optimized approach.
KW - Data Placement
KW - Domain Wall Memory
KW - Heuristic
KW - Optimization
KW - Shift Operation
UR - https://www.scopus.com/pages/publications/84944104276
U2 - 10.1145/2744769.2744883
DO - 10.1145/2744769.2744883
M3 - 会议稿件
AN - SCOPUS:84944104276
T3 - Proceedings - Design Automation Conference
BT - 2015 52nd ACM/EDAC/IEEE Design Automation Conference, DAC 2015
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 52nd ACM/EDAC/IEEE Design Automation Conference, DAC 2015
Y2 - 8 June 2015 through 12 June 2015
ER -