Optimizing Data Placement for Hybrid SPM with SRAM and Racetrack Memory

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9 Scopus citations

Abstract

In this paper, a novel hybrid scratchpad memory (SPM) with SRAM and racetrack memory (RM) is proposed. The basic idea is to smartly place data on SPM by taking the advantages of these two memories. First, a metric is proposed to represent the access cost of data; Second, a data placement scheme is proposed based on the metric; Finally, to maximize the size of SPM, a scheme is further proposed to minimize the size of SRAM. Experimental results show that the proposed scheme reduces the shift operations of RM by 80.12% and reduces the cost of SPM by 80.72% with only 17.63% SRAM compared with a baseline SPM with pure RM.

Original languageEnglish
Title of host publicationProceedings - 2020 IEEE 38th International Conference on Computer Design, ICCD 2020
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages409-416
Number of pages8
ISBN (Electronic)9781728197104
DOIs
StatePublished - Oct 2020
Event38th IEEE International Conference on Computer Design, ICCD 2020 - Hartford, United States
Duration: 18 Oct 202021 Oct 2020

Publication series

NameProceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
Volume2020-October
ISSN (Print)1063-6404

Conference

Conference38th IEEE International Conference on Computer Design, ICCD 2020
Country/TerritoryUnited States
CityHartford
Period18/10/2021/10/20

Keywords

  • SRAM
  • data placement
  • hybrid scratchpad memory (SPM)
  • racetrack memory
  • shift operation

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