Optimal scheduling to minimize non-volatile memory access time with hardware cache

Wei Che Tseng; Chun Jason Xue; Qingfeng Zhuge; Jingtong Hu; Edwin H.M. Sha

doi:10.1109/VLSISOC.2010.5642609

Optimal scheduling to minimize non-volatile memory access time with hardware cache

Wei Che Tseng^*
, Chun Jason Xue
, Qingfeng Zhuge
, Jingtong Hu
, Edwin H.M. Sha

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

18 Scopus citations

Abstract

In power and size sensitive embedded systems, flash memory and phase change memory are replacing DRAM as the main memory. Unfortunately, these technologies are limited by their endurance and long write latencies. To minimize the main memory access time, we optimally schedule tasks by an ILP formulation that can be generally applied to other main memory technologies, including DRAM. We also present a heuristic, Wander Scheduling, to solve larger instances in a reasonable amount of time. Our experimental results show that when compared with list scheduling, Wander Scheduling can reduce memory access times by an average of 40.73% and increase the lifetime of flash and phase change memory by 82.56%.

Original language	English
Title of host publication	Proceedings of the 2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2010
Pages	131-136
Number of pages	6
DOIs	https://doi.org/10.1109/VLSISOC.2010.5642609
State	Published - 2010
Externally published	Yes
Event	2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2010 - Madrid, Spain Duration: 27 Sep 2010 → 29 Sep 2010

Publication series

Name	Proceedings of the 2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2010

Conference

Conference	2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2010
Country/Territory	Spain
City	Madrid
Period	27/09/10 → 29/09/10

Access to Document

10.1109/VLSISOC.2010.5642609

Cite this

Tseng, W. C., Xue, C. J., Zhuge, Q., Hu, J., & Sha, E. H. M. (2010). Optimal scheduling to minimize non-volatile memory access time with hardware cache. In Proceedings of the 2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2010 (pp. 131-136). Article 5642609 (Proceedings of the 2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2010). https://doi.org/10.1109/VLSISOC.2010.5642609

Tseng, Wei Che ; Xue, Chun Jason ; Zhuge, Qingfeng et al. / Optimal scheduling to minimize non-volatile memory access time with hardware cache. Proceedings of the 2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2010. 2010. pp. 131-136 (Proceedings of the 2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2010).

@inproceedings{331785bc597d4fe889d4672dd8b740a3,

title = "Optimal scheduling to minimize non-volatile memory access time with hardware cache",

abstract = "In power and size sensitive embedded systems, flash memory and phase change memory are replacing DRAM as the main memory. Unfortunately, these technologies are limited by their endurance and long write latencies. To minimize the main memory access time, we optimally schedule tasks by an ILP formulation that can be generally applied to other main memory technologies, including DRAM. We also present a heuristic, Wander Scheduling, to solve larger instances in a reasonable amount of time. Our experimental results show that when compared with list scheduling, Wander Scheduling can reduce memory access times by an average of 40.73\% and increase the lifetime of flash and phase change memory by 82.56\%.",

author = "Tseng, \{Wei Che\} and Xue, \{Chun Jason\} and Qingfeng Zhuge and Jingtong Hu and Sha, \{Edwin H.M.\}",

year = "2010",

doi = "10.1109/VLSISOC.2010.5642609",

language = "英语",

isbn = "9781424464708",

series = "Proceedings of the 2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2010",

pages = "131--136",

booktitle = "Proceedings of the 2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2010",

note = "2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2010 ; Conference date: 27-09-2010 Through 29-09-2010",

}

Tseng, WC, Xue, CJ, Zhuge, Q, Hu, J & Sha, EHM 2010, Optimal scheduling to minimize non-volatile memory access time with hardware cache. in Proceedings of the 2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2010., 5642609, Proceedings of the 2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2010, pp. 131-136, 2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2010, Madrid, Spain, 27/09/10. https://doi.org/10.1109/VLSISOC.2010.5642609

Optimal scheduling to minimize non-volatile memory access time with hardware cache. / Tseng, Wei Che; Xue, Chun Jason; Zhuge, Qingfeng et al.
Proceedings of the 2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2010. 2010. p. 131-136 5642609 (Proceedings of the 2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2010).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Optimal scheduling to minimize non-volatile memory access time with hardware cache

AU - Tseng, Wei Che

AU - Xue, Chun Jason

AU - Zhuge, Qingfeng

AU - Hu, Jingtong

AU - Sha, Edwin H.M.

PY - 2010

Y1 - 2010

N2 - In power and size sensitive embedded systems, flash memory and phase change memory are replacing DRAM as the main memory. Unfortunately, these technologies are limited by their endurance and long write latencies. To minimize the main memory access time, we optimally schedule tasks by an ILP formulation that can be generally applied to other main memory technologies, including DRAM. We also present a heuristic, Wander Scheduling, to solve larger instances in a reasonable amount of time. Our experimental results show that when compared with list scheduling, Wander Scheduling can reduce memory access times by an average of 40.73% and increase the lifetime of flash and phase change memory by 82.56%.

AB - In power and size sensitive embedded systems, flash memory and phase change memory are replacing DRAM as the main memory. Unfortunately, these technologies are limited by their endurance and long write latencies. To minimize the main memory access time, we optimally schedule tasks by an ILP formulation that can be generally applied to other main memory technologies, including DRAM. We also present a heuristic, Wander Scheduling, to solve larger instances in a reasonable amount of time. Our experimental results show that when compared with list scheduling, Wander Scheduling can reduce memory access times by an average of 40.73% and increase the lifetime of flash and phase change memory by 82.56%.

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DO - 10.1109/VLSISOC.2010.5642609

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Tseng WC, Xue CJ, Zhuge Q, Hu J, Sha EHM. Optimal scheduling to minimize non-volatile memory access time with hardware cache. In Proceedings of the 2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2010. 2010. p. 131-136. 5642609. (Proceedings of the 2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2010). doi: 10.1109/VLSISOC.2010.5642609

Optimal scheduling to minimize non-volatile memory access time with hardware cache

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