Optimal partitioning and balanced scheduling with the maximal overlap of data footprints

Z. Wang; E. H.M. Sha; Y. Wang

doi:10.1145/368122.368155

Optimal partitioning and balanced scheduling with the maximal overlap of data footprints

Z. Wang^*
, E. H.M. Sha
, Y. Wang

^*Corresponding author for this work

University of Notre Dame

Research output: Contribution to journal › Conference article › peer-review

1 Scopus citations

Abstract

The paper proposes a scheme to tolerate the slow memory access latency for loop intensive applications in the system with memory hierarchy. The scheme takes into consideration of both the intermediate data and maximal overlap of data footprints for initial data. Furthermore, a schedule is presented to balance the ALU computation and memory operations. The memory requirement under such schedule is calculated. This schedule's improvement in total execution time is approximately 20% over existing methods.

Original language	English
Pages (from-to)	31-36
Number of pages	6
Journal	Proceedings of the IEEE Great Lakes Symposium on VLSI
DOIs	https://doi.org/10.1145/368122.368155
State	Published - 2001
Externally published	Yes
Event	11th Great Lakes Sysmposium on VLSI (GLSVLSI 2001) - West Lafayette, IN, United States Duration: 22 Mar 2001 → 23 Mar 2001

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abstract = "The paper proposes a scheme to tolerate the slow memory access latency for loop intensive applications in the system with memory hierarchy. The scheme takes into consideration of both the intermediate data and maximal overlap of data footprints for initial data. Furthermore, a schedule is presented to balance the ALU computation and memory operations. The memory requirement under such schedule is calculated. This schedule's improvement in total execution time is approximately 20\% over existing methods.",

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AB - The paper proposes a scheme to tolerate the slow memory access latency for loop intensive applications in the system with memory hierarchy. The scheme takes into consideration of both the intermediate data and maximal overlap of data footprints for initial data. Furthermore, a schedule is presented to balance the ALU computation and memory operations. The memory requirement under such schedule is calculated. This schedule's improvement in total execution time is approximately 20% over existing methods.

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T2 - 11th Great Lakes Sysmposium on VLSI (GLSVLSI 2001)

Y2 - 22 March 2001 through 23 March 2001

ER -

Optimal partitioning and balanced scheduling with the maximal overlap of data footprints

Abstract

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