TY - JOUR
T1 - Novel Triple-Gate Nanosheet RFET With Embedded SiGe Surrounding Channel for Enhanced On-State Current
AU - Zou, Xinyu
AU - Zhou, Yuhao
AU - Gong, Fu
AU - Liu, Ziyu
AU - Li, Xiaojin
AU - Shen, Yang
AU - Ye, Bingyi
AU - Zhang, Yuhang
AU - Shi, Yanling
AU - Sun, Yabin
N1 - Publisher Copyright:
© 1963-2012 IEEE.
PY - 2026
Y1 - 2026
N2 - In this study, a novel triple-gate nanosheet reconfigurable field-effect transistor (RFET) featuring an embedded SiGe layer conformally surrounding the silicon channel (ESCRFET) beneath the control gate (CG) was proposed. The bandgap offset between SiGe and Si is utilized to modulate the energy band profile and optimize carrier injection in both n- and p-type operation modes. Compared to the traditional triple-gate RFET (TG-RFET), the proposed ESCRFET achieves 50.2% and 82.2% enhancement in Ion for n- and p-type devices, respectively, while maintaining comparable subthreshold swing characteristics. A neural-network-based compact model is developed to accurately reproduce the electrical characteristics, with an average error of less than 3%, enabling efficient SPICE-level circuit simulation. Circuit-level simulations of nor, AOI, and 1-bit full-adder circuits demonstrate that ESCRFET significantly reduces propagation delay, achieving a 40%–60% faster response compared with the TG-RFET, while also lowering the total transistor count from 28 to 18, corresponding to a 36% reduction. These results confirm the superior electrical performance and scalability of the ESCRFET for future reconfigurable logic and arithmetic circuit applications.
AB - In this study, a novel triple-gate nanosheet reconfigurable field-effect transistor (RFET) featuring an embedded SiGe layer conformally surrounding the silicon channel (ESCRFET) beneath the control gate (CG) was proposed. The bandgap offset between SiGe and Si is utilized to modulate the energy band profile and optimize carrier injection in both n- and p-type operation modes. Compared to the traditional triple-gate RFET (TG-RFET), the proposed ESCRFET achieves 50.2% and 82.2% enhancement in Ion for n- and p-type devices, respectively, while maintaining comparable subthreshold swing characteristics. A neural-network-based compact model is developed to accurately reproduce the electrical characteristics, with an average error of less than 3%, enabling efficient SPICE-level circuit simulation. Circuit-level simulations of nor, AOI, and 1-bit full-adder circuits demonstrate that ESCRFET significantly reduces propagation delay, achieving a 40%–60% faster response compared with the TG-RFET, while also lowering the total transistor count from 28 to 18, corresponding to a 36% reduction. These results confirm the superior electrical performance and scalability of the ESCRFET for future reconfigurable logic and arithmetic circuit applications.
KW - 1-bit full adder
KW - embedded SiGe layer surrounding the silicon channel (ESCRFET)
KW - neural-network
KW - ON-state current
UR - https://www.scopus.com/pages/publications/105027744931
U2 - 10.1109/TED.2025.3650575
DO - 10.1109/TED.2025.3650575
M3 - 文章
AN - SCOPUS:105027744931
SN - 0018-9383
JO - IEEE Transactions on Electron Devices
JF - IEEE Transactions on Electron Devices
ER -