TY - JOUR
T1 - Novel Reconfigurable Transistor with Extended Source/Drain beyond 3 nm Technology Node
AU - Ye, Hongbo
AU - Hu, Junfeng
AU - Liu, Ziyu
AU - Wang, Chao
AU - Li, Xiaojin
AU - Shi, Yanling
AU - Mao, Zhigang
AU - Sun, Yabin
N1 - Publisher Copyright:
© 1963-2012 IEEE.
PY - 2024/4/1
Y1 - 2024/4/1
N2 - In this work, a novel stacked nanosheet reconfigurable field effect transistor with extended source/drain (ESD-NSRFET) is proposed to improve ON-current ({I} _{ \mathrm{\scriptscriptstyle ON}}$ ), where an additional extended source/drain is intersected between the vertically stacked nanosheets. Compared to the conventional nanosheet RFET (NSRFET), {I} _{ \mathrm{\scriptscriptstyle ON}}$ of proposed ESD-NSRFET with 4 nm extended source is demonstrated to improve by 176\times $ and 80\times $ for n-type and p-type program, respectively. Geometry parameters like extended source/drain length {L} _{\text {ESD}}$ , nanosheet width {W} _{\text {NS}}$ , and nanosheet thickness {T} _{\text {NS}}$ are investigated in point of {I} _{ \mathrm{\scriptscriptstyle ON}}$. Considering the trade-off between increased tunneling strength and degraded parasitic source resistance, {L} _{\text {ESD}}$ in ESD-NSRFET should be carefully designed to obtain optimal current. The underlying physical mechanism is also discussed in detail.
AB - In this work, a novel stacked nanosheet reconfigurable field effect transistor with extended source/drain (ESD-NSRFET) is proposed to improve ON-current ({I} _{ \mathrm{\scriptscriptstyle ON}}$ ), where an additional extended source/drain is intersected between the vertically stacked nanosheets. Compared to the conventional nanosheet RFET (NSRFET), {I} _{ \mathrm{\scriptscriptstyle ON}}$ of proposed ESD-NSRFET with 4 nm extended source is demonstrated to improve by 176\times $ and 80\times $ for n-type and p-type program, respectively. Geometry parameters like extended source/drain length {L} _{\text {ESD}}$ , nanosheet width {W} _{\text {NS}}$ , and nanosheet thickness {T} _{\text {NS}}$ are investigated in point of {I} _{ \mathrm{\scriptscriptstyle ON}}$. Considering the trade-off between increased tunneling strength and degraded parasitic source resistance, {L} _{\text {ESD}}$ in ESD-NSRFET should be carefully designed to obtain optimal current. The underlying physical mechanism is also discussed in detail.
KW - Extended source/drain
KW - line tunneling
KW - reconfigurable field-effect transistor (RFET)
UR - https://www.scopus.com/pages/publications/85186098289
U2 - 10.1109/TED.2024.3359581
DO - 10.1109/TED.2024.3359581
M3 - 文章
AN - SCOPUS:85186098289
SN - 0018-9383
VL - 71
SP - 2265
EP - 2270
JO - IEEE Transactions on Electron Devices
JF - IEEE Transactions on Electron Devices
IS - 4
ER -