TY - JOUR
T1 - Novel Reconfigurable Field-Effect Transistor with Surrounded Source/Drain to Improve On-State Current
AU - Hu, Junfeng
AU - Wang, Chao
AU - Sun, Yabin
AU - Liu, Ziyu
AU - Li, Xiaojin
AU - Shi, Yanling
N1 - Publisher Copyright:
© 1963-2012 IEEE.
PY - 2024/1/1
Y1 - 2024/1/1
N2 - In this article, a novel reconfigurable field-effect transistor with surrounded source and drain (SSDRFET) is proposed to improve ON-state current. Compared to the conventional nanosheet reconfigurable transistor (NSRFET), the source and drain in SSDRFET are surrounded by a silicon channel and metal gate, and a higher tunneling probability and gate control ability are obtained. And, 5.52 and 4.92 times improvement of ON-state current (ION) separately exists for n-type and p-type SSDRFET. The performance under different geometry parameters, including source/drain diameter (Dsd), source/drain distance (Lsd), control gate (CG) length, and program gate (PG) length are investigated by using 3-D TCAD simulation. The results show that size parameters need to be selected carefully to get a better performance. Furthermore, the reduced gate capacitance and improved ION contribute to the more advantageous inverter based on SSDRFET, reducing about 70% of propagation delay. The underlying physical mechanisms are discussed in detail.
AB - In this article, a novel reconfigurable field-effect transistor with surrounded source and drain (SSDRFET) is proposed to improve ON-state current. Compared to the conventional nanosheet reconfigurable transistor (NSRFET), the source and drain in SSDRFET are surrounded by a silicon channel and metal gate, and a higher tunneling probability and gate control ability are obtained. And, 5.52 and 4.92 times improvement of ON-state current (ION) separately exists for n-type and p-type SSDRFET. The performance under different geometry parameters, including source/drain diameter (Dsd), source/drain distance (Lsd), control gate (CG) length, and program gate (PG) length are investigated by using 3-D TCAD simulation. The results show that size parameters need to be selected carefully to get a better performance. Furthermore, the reduced gate capacitance and improved ION contribute to the more advantageous inverter based on SSDRFET, reducing about 70% of propagation delay. The underlying physical mechanisms are discussed in detail.
KW - Gate-all-around (GAA)
KW - ON-state current
KW - Schottky junction
KW - nanosheet
KW - reconfigurable field-effect transistor (RFET)
UR - https://www.scopus.com/pages/publications/85182402802
U2 - 10.1109/TED.2023.3335332
DO - 10.1109/TED.2023.3335332
M3 - 文章
AN - SCOPUS:85182402802
SN - 0018-9383
VL - 71
SP - 873
EP - 878
JO - IEEE Transactions on Electron Devices
JF - IEEE Transactions on Electron Devices
IS - 1
ER -