TY - GEN
T1 - Novel Radiation Hardened Latch Design with Cost-Effectiveness for Safety-Critical Terrestrial Applications
AU - Yan, Aibin
AU - Wu, Zhen
AU - Lu, Lu
AU - Chen, Zhili
AU - Song, Jie
AU - Ying, Zuobin
AU - Girard, Patrick
AU - Wen, Xiaoqing
N1 - Publisher Copyright:
© 2019 IEEE.
PY - 2019/12
Y1 - 2019/12
N2 - To meet the requirements of both cost-effectiveness and high reliability for safety-critical terrestrial applications, this paper proposes a novel radiation hardened latch design, namely HLCRT. The HLCRT latch mainly consists of a single-node-upset self-recoverable cell, a 3-input C-element, and an inverter. If any two inputs of the C-element suffer from a double-node-upset (DNU), or if one node inside the cell together with another node outside the cell suffer from a DNU, the latch still has correct values on its output node, i.e., the latch is effectively DNU hardened. Simulation results demonstrate the DNU tolerance of the proposed latch. Moreover, due to the use of fewer transistors, clock gating technologies, and a high-speed path, the proposed latch saves about 444.80% delay, 150.50% power, 72.66% area, and 2029.63% delay-power-area product on average, compared with state-of-the-art DNU hardened latch designs.
AB - To meet the requirements of both cost-effectiveness and high reliability for safety-critical terrestrial applications, this paper proposes a novel radiation hardened latch design, namely HLCRT. The HLCRT latch mainly consists of a single-node-upset self-recoverable cell, a 3-input C-element, and an inverter. If any two inputs of the C-element suffer from a double-node-upset (DNU), or if one node inside the cell together with another node outside the cell suffer from a DNU, the latch still has correct values on its output node, i.e., the latch is effectively DNU hardened. Simulation results demonstrate the DNU tolerance of the proposed latch. Moreover, due to the use of fewer transistors, clock gating technologies, and a high-speed path, the proposed latch saves about 444.80% delay, 150.50% power, 72.66% area, and 2029.63% delay-power-area product on average, compared with state-of-the-art DNU hardened latch designs.
KW - Radiation hardening
KW - cost effectiveness
KW - double node upset
KW - latch design
KW - soft error
UR - https://www.scopus.com/pages/publications/85078359545
U2 - 10.1109/ATS47505.2019.000-2
DO - 10.1109/ATS47505.2019.000-2
M3 - 会议稿件
AN - SCOPUS:85078359545
T3 - Proceedings of the Asian Test Symposium
SP - 43
EP - 48
BT - Proceedings - 2019 IEEE 28th Asian Test Symposium, ATS 2019
PB - IEEE Computer Society
T2 - 28th IEEE Asian Test Symposium, ATS 2019
Y2 - 10 December 2019 through 13 December 2019
ER -