Modeling and simulation for NBTI-considered path delay prediction in logical circuit

Yao Lin; Xiaojin Li; Yanling Shi

doi:10.1109/IWJT.2014.6842033

Modeling and simulation for NBTI-considered path delay prediction in logical circuit

Yao Lin
, Xiaojin Li^*
, Yanling Shi

^*Corresponding author for this work

School of Communication and Electronic Engineering

East China Normal University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

NBTI (Negative Bias Temperature Instability) is a major concern in long-time circuit performance. In this paper, NBTI degradation models of basic logic gates have been developed based on the conventional reaction-diffusion (R-D) model which is used to predict the threshold voltage shift (ΔV _TH) of p-type MOSFET. Besides load capacitance (C_L), input slew rate (t_i) and supply voltage (V_DD), ΔV _TH versus gate delay degradation of NAND, INV, and NOR have been evaluated and approximated by second-order polynomials. Furthermore, a method to calculate the degradation of circuit speed over a long period of time given input switching rate, duty factor and power supply, is built up. Finally, the effectiveness of the proposed has been demonstrated with the ISCAS'85 benchmark circuit.

Original language	English
Title of host publication	2014 International Workshop on Junction Technology, IWJT 2014
Publisher	IEEE Computer Society
Pages	69-72
Number of pages	4
ISBN (Print)	9781479936274
DOIs	https://doi.org/10.1109/IWJT.2014.6842033
State	Published - 2014
Event	14th International Workshop on Junction Technology, IWJT 2014 - Shanghai, China Duration: 18 May 2014 → 20 May 2014

Publication series

Name	2014 International Workshop on Junction Technology, IWJT 2014

Conference

Conference	14th International Workshop on Junction Technology, IWJT 2014
Country/Territory	China
City	Shanghai
Period	18/05/14 → 20/05/14

Access to Document

10.1109/IWJT.2014.6842033

Cite this

@inproceedings{1b722c70773b4e6fa50b3769bd24fcfe,

title = "Modeling and simulation for NBTI-considered path delay prediction in logical circuit",

abstract = "NBTI (Negative Bias Temperature Instability) is a major concern in long-time circuit performance. In this paper, NBTI degradation models of basic logic gates have been developed based on the conventional reaction-diffusion (R-D) model which is used to predict the threshold voltage shift (ΔV TH) of p-type MOSFET. Besides load capacitance (CL), input slew rate (ti) and supply voltage (VDD), ΔV TH versus gate delay degradation of NAND, INV, and NOR have been evaluated and approximated by second-order polynomials. Furthermore, a method to calculate the degradation of circuit speed over a long period of time given input switching rate, duty factor and power supply, is built up. Finally, the effectiveness of the proposed has been demonstrated with the ISCAS'85 benchmark circuit.",

author = "Yao Lin and Xiaojin Li and Yanling Shi",

year = "2014",

doi = "10.1109/IWJT.2014.6842033",

language = "英语",

isbn = "9781479936274",

series = "2014 International Workshop on Junction Technology, IWJT 2014",

publisher = "IEEE Computer Society",

pages = "69--72",

booktitle = "2014 International Workshop on Junction Technology, IWJT 2014",

address = "美国",

note = "14th International Workshop on Junction Technology, IWJT 2014 ; Conference date: 18-05-2014 Through 20-05-2014",

}

Lin, Y, Li, X & Shi, Y 2014, Modeling and simulation for NBTI-considered path delay prediction in logical circuit. in 2014 International Workshop on Junction Technology, IWJT 2014., 6842033, 2014 International Workshop on Junction Technology, IWJT 2014, IEEE Computer Society, pp. 69-72, 14th International Workshop on Junction Technology, IWJT 2014, Shanghai, China, 18/05/14. https://doi.org/10.1109/IWJT.2014.6842033

Modeling and simulation for NBTI-considered path delay prediction in logical circuit. / Lin, Yao; Li, Xiaojin; Shi, Yanling.
2014 International Workshop on Junction Technology, IWJT 2014. IEEE Computer Society, 2014. p. 69-72 6842033 (2014 International Workshop on Junction Technology, IWJT 2014).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Modeling and simulation for NBTI-considered path delay prediction in logical circuit

AU - Lin, Yao

AU - Li, Xiaojin

AU - Shi, Yanling

PY - 2014

Y1 - 2014

N2 - NBTI (Negative Bias Temperature Instability) is a major concern in long-time circuit performance. In this paper, NBTI degradation models of basic logic gates have been developed based on the conventional reaction-diffusion (R-D) model which is used to predict the threshold voltage shift (ΔV TH) of p-type MOSFET. Besides load capacitance (CL), input slew rate (ti) and supply voltage (VDD), ΔV TH versus gate delay degradation of NAND, INV, and NOR have been evaluated and approximated by second-order polynomials. Furthermore, a method to calculate the degradation of circuit speed over a long period of time given input switching rate, duty factor and power supply, is built up. Finally, the effectiveness of the proposed has been demonstrated with the ISCAS'85 benchmark circuit.

AB - NBTI (Negative Bias Temperature Instability) is a major concern in long-time circuit performance. In this paper, NBTI degradation models of basic logic gates have been developed based on the conventional reaction-diffusion (R-D) model which is used to predict the threshold voltage shift (ΔV TH) of p-type MOSFET. Besides load capacitance (CL), input slew rate (ti) and supply voltage (VDD), ΔV TH versus gate delay degradation of NAND, INV, and NOR have been evaluated and approximated by second-order polynomials. Furthermore, a method to calculate the degradation of circuit speed over a long period of time given input switching rate, duty factor and power supply, is built up. Finally, the effectiveness of the proposed has been demonstrated with the ISCAS'85 benchmark circuit.

UR - https://www.scopus.com/pages/publications/84904683204

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DO - 10.1109/IWJT.2014.6842033

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SN - 9781479936274

T3 - 2014 International Workshop on Junction Technology, IWJT 2014

SP - 69

EP - 72

BT - 2014 International Workshop on Junction Technology, IWJT 2014

PB - IEEE Computer Society

T2 - 14th International Workshop on Junction Technology, IWJT 2014

Y2 - 18 May 2014 through 20 May 2014

ER -

Modeling and simulation for NBTI-considered path delay prediction in logical circuit

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