Minimizing memory access schedule for memories

  • Jingtong Hu*
  • , Chun Jason Xue
  • , Wei Che Tseng
  • , Meikang Qiu
  • , Yingchao Zhao
  • , Edwin H.M. Sha
  • *Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

3 Scopus citations

Abstract

According to the characteristics of the "3-D" structure of contemporary DRAM chips, the Row First Column Ordered (RFCO) algorithm is proposed in this paper to minimize memory access schedule length. In memory systems with a single memory controller, assuming that the memory access trace is known before scheduling, the RFCO algorithm can generate schedules which are 7.89% shorter than burst scheduling [12] on average. If memory accesses are coming to the single memory controller in real time, the RFCO algorithm can generate schedules which are 8.03% shorter than burst scheduling on average.

Original languageEnglish
Title of host publicationICPADS '09 - 15th International Conference on Parallel and Distributed Systems
Pages104-111
Number of pages8
DOIs
StatePublished - 2009
Externally publishedYes
Event15th International Conference on Parallel and Distributed Systems, ICPADS '09 - Shenzhen, Guangdong, China
Duration: 8 Dec 200911 Dec 2009

Publication series

NameProceedings of the International Conference on Parallel and Distributed Systems - ICPADS
ISSN (Print)1521-9097

Conference

Conference15th International Conference on Parallel and Distributed Systems, ICPADS '09
Country/TerritoryChina
CityShenzhen, Guangdong
Period8/12/0911/12/09

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