Minimizing cell-to-cell interference by exploiting differential bit impact characteristics of scaled MLC NAND flash memories

Appealed by the market, flash memory density is being increasingly improved, and the technology scale is being reduced. Currently, scaled multi-level-cell (MLC) flash memory has been the dominant in the global flash memory markets. However, the reliability of MLC flash memory becomes the urgent challenge, where cell-to-cell interference has been well recognized as the major error source. In this work, we propose to minimize cell-to-cell interference through exploiting the differential impacts on the multiple-bit of MLC flash memories. MLC flash memory generally has two or more bits per cell, such as 2-bit/cell or 4-bit/cell, which can be differentially interfered by neighboring cell programming. Based on the understanding of the programming characteristics of MLC flash memory, we found that higher-order bits can be higher interfered and be more significant interference sources. In order to understand the characteristics of cell-tocell interference on the multiple bits, we first present cell-to-cell interference models for multiple bits, respectively. Then based on the model, a state mapping scheme is designed to minimize cell-to-cell interference through mapping the states of high-order bits. The mapping scheme is motivated by the recent studies on the cell-to-cell interference characteristics of the multiple cell states of flash memory, where different states have varying interferences. In this case, high-order bits should be mapped from high interference states to a low one. A series of experiments show that the proposed scheme is efficient on reducing cell-to-cell interference with negligible overhead.