TY - GEN
T1 - Migration-aware loop retiming for STT-RAM based hybrid cache for embedded systems
AU - Qiu, Keni
AU - Zhao, Mengying
AU - Fu, Chenchen
AU - Shi, Liang
AU - Xue, Chun Jason
PY - 2013
Y1 - 2013
N2 - In hybrid cache architecture consisting of both STT-RAM and SRAM, migration based techniques have been proposed. The migration technique dynamically moves write-intensive and read-intensive data between STT-RAM and SRAM to explore the advantage of hybrid cache. Meanwhile, migrations induce extra read and write overhead during data movements. For loops with intensive data array operations, we observe that migration overhead is significant and migrations closely correlate to the interleaved read and write access pattern in a memory block. This paper proposes a loop retiming framework to reduce the migration overhead by changing the interleaved memory access pattern. The experimental results show that with the proposed method, migrations are significantly reduced without any hardware modification. As a result, energy efficiency and performance of hybrid cache can be improved.
AB - In hybrid cache architecture consisting of both STT-RAM and SRAM, migration based techniques have been proposed. The migration technique dynamically moves write-intensive and read-intensive data between STT-RAM and SRAM to explore the advantage of hybrid cache. Meanwhile, migrations induce extra read and write overhead during data movements. For loops with intensive data array operations, we observe that migration overhead is significant and migrations closely correlate to the interleaved read and write access pattern in a memory block. This paper proposes a loop retiming framework to reduce the migration overhead by changing the interleaved memory access pattern. The experimental results show that with the proposed method, migrations are significantly reduced without any hardware modification. As a result, energy efficiency and performance of hybrid cache can be improved.
UR - https://www.scopus.com/pages/publications/84883331158
U2 - 10.1109/ASAP.2013.6567555
DO - 10.1109/ASAP.2013.6567555
M3 - 会议稿件
AN - SCOPUS:84883331158
SN - 9781479904921
T3 - Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors
SP - 83
EP - 86
BT - ASAP 2013 - Proceedings of the 2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2013
Y2 - 5 June 2013 through 7 June 2013
ER -
