TY - GEN
T1 - Memory access aware mapping for networks-on-chip
AU - Jin, Xi
AU - Guan, Nan
AU - Deng, Qingxu
AU - Yi, Wang
PY - 2011
Y1 - 2011
N2 - Networks-on-Chip (NoC) has been introduced to offer high on-chip communication bandwidth for large-scale multi-core systems. However, the communication bandwidth between NoC chips and off-chip memories is relatively low, which seriously limits the overall system performance. So optimizing the off-chip memory communication efficiency is a crucial issue in the NoC system design flow. In this paper, we present a memory access aware mapping algorithm for NoC, which explores SDRAM access parallelization in order to offer higher off-chip memory communication efficiency, and eventually achieve higher overall system performance. To the best of our knowledge, this is the first work to consider off-chip memory communication efficiency in application mapping on NoC. Experimental results showed that, comparing with classical NoC mapping algorithms, our algorithm can significantly improve the memory utilization and overall system throughput (on average 60% improvement).
AB - Networks-on-Chip (NoC) has been introduced to offer high on-chip communication bandwidth for large-scale multi-core systems. However, the communication bandwidth between NoC chips and off-chip memories is relatively low, which seriously limits the overall system performance. So optimizing the off-chip memory communication efficiency is a crucial issue in the NoC system design flow. In this paper, we present a memory access aware mapping algorithm for NoC, which explores SDRAM access parallelization in order to offer higher off-chip memory communication efficiency, and eventually achieve higher overall system performance. To the best of our knowledge, this is the first work to consider off-chip memory communication efficiency in application mapping on NoC. Experimental results showed that, comparing with classical NoC mapping algorithms, our algorithm can significantly improve the memory utilization and overall system throughput (on average 60% improvement).
UR - https://www.scopus.com/pages/publications/84855538473
U2 - 10.1109/RTCSA.2011.31
DO - 10.1109/RTCSA.2011.31
M3 - 会议稿件
AN - SCOPUS:84855538473
SN - 9780769545028
T3 - Proceedings - 17th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2011
SP - 339
EP - 348
BT - Proceedings - 17th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2011
T2 - 17th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2011
Y2 - 28 August 2011 through 31 August 2011
ER -