TY - GEN
T1 - Maximizing IO performance via conflict reduction for flash memory storage systems
AU - Li, Qiao
AU - Shi, Liang
AU - Gao, Congming
AU - Wu, Kaijie
AU - Xue, Chun Jason
AU - Zhuge, Qingfeng
AU - Sha, Edwin H.M.
N1 - Publisher Copyright:
© 2015 EDAA.
PY - 2015/4/22
Y1 - 2015/4/22
N2 - Flash memory has been widely deployed during the recent years with the improvement of bit density and technology scaling. However, a significant performance degradation is also introduced with the development trend. The latency of IO requests on flash memory storage systems is composed of access conflict latency, data transfer latency, flash chip access latency and ECC encoding/decoding latency. Studies show that the access conflict latency, which is mainly induced by the slow transfer latency and access latency, has become the dominate part of the IO latency, especially for IO intensive applications. This paper proposes to reduce the flash access conflict latency through the reduction of the transfer and flash access latencies. A latency model is built to construct the relationship among the transfer latency and access latency based on the reliability characteristics of flash memory. Simulation experiments show that the proposed approach achieves significant performance improvement.
AB - Flash memory has been widely deployed during the recent years with the improvement of bit density and technology scaling. However, a significant performance degradation is also introduced with the development trend. The latency of IO requests on flash memory storage systems is composed of access conflict latency, data transfer latency, flash chip access latency and ECC encoding/decoding latency. Studies show that the access conflict latency, which is mainly induced by the slow transfer latency and access latency, has become the dominate part of the IO latency, especially for IO intensive applications. This paper proposes to reduce the flash access conflict latency through the reduction of the transfer and flash access latencies. A latency model is built to construct the relationship among the transfer latency and access latency based on the reliability characteristics of flash memory. Simulation experiments show that the proposed approach achieves significant performance improvement.
UR - https://www.scopus.com/pages/publications/84945966494
U2 - 10.7873/date.2015.0078
DO - 10.7873/date.2015.0078
M3 - 会议稿件
AN - SCOPUS:84945966494
T3 - Proceedings -Design, Automation and Test in Europe, DATE
SP - 904
EP - 907
BT - Proceedings of the 2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015
Y2 - 9 March 2015 through 13 March 2015
ER -