TY - GEN
T1 - MALTS
T2 - 2025 International Symposium of Electronics Design Automation, ISEDA 2025
AU - Dou, Jiaqi
AU - Zhang, Jianing
AU - Ye, Bingyi
AU - Shen, Yang
AU - Li, Xiaojin
AU - Shi, Yanling
AU - Zhang, Yuhang
AU - Sun, Yabin
N1 - Publisher Copyright:
© 2025 IEEE.
PY - 2025
Y1 - 2025
N2 - The demand for efficient 3D modeling in Technology Computer-Aided Design (TCAD) simulations has surged, driven by the need for rapid device performance evaluation and Design Technology Co-Optimization (DTCO). Traditional TCAD modeling involves time-consuming process emulation and complex script editing, which limits the scope within single-device simulations and hinders scalability. To address these challenges, this paper introduces MALTS, a multi-agent large language model-based layout-to-TCAD structure synthesizer. The proposed framework takes industrial layout files (e.g., GDSII) and process information as inputs, and directly generates simulation-ready definitions in standard TCAD syntax, eliminating the need for iterative process emulation and manual script adjustments typically required in conventional workflows. By decomposing the synthesis process and assigning each phase to a specialized LLM agent, MALTS mitigates the "long-context forgetting"problem, enabling efficient generation of complex structures and gate-level TCAD models. Experimental results demonstrate that the proposed framework provides an automated solution for analyzing the impact of various physical layout designs and process details on electrical characteristics, facilitating rapid design space exploration in the DTCO process.
AB - The demand for efficient 3D modeling in Technology Computer-Aided Design (TCAD) simulations has surged, driven by the need for rapid device performance evaluation and Design Technology Co-Optimization (DTCO). Traditional TCAD modeling involves time-consuming process emulation and complex script editing, which limits the scope within single-device simulations and hinders scalability. To address these challenges, this paper introduces MALTS, a multi-agent large language model-based layout-to-TCAD structure synthesizer. The proposed framework takes industrial layout files (e.g., GDSII) and process information as inputs, and directly generates simulation-ready definitions in standard TCAD syntax, eliminating the need for iterative process emulation and manual script adjustments typically required in conventional workflows. By decomposing the synthesis process and assigning each phase to a specialized LLM agent, MALTS mitigates the "long-context forgetting"problem, enabling efficient generation of complex structures and gate-level TCAD models. Experimental results demonstrate that the proposed framework provides an automated solution for analyzing the impact of various physical layout designs and process details on electrical characteristics, facilitating rapid design space exploration in the DTCO process.
KW - TCAD
KW - design-technology co-optimization
KW - large language model
KW - multi-agent
UR - https://www.scopus.com/pages/publications/105014238634
U2 - 10.1109/ISEDA65950.2025.11101083
DO - 10.1109/ISEDA65950.2025.11101083
M3 - 会议稿件
AN - SCOPUS:105014238634
T3 - 2025 International Symposium of Electronics Design Automation, ISEDA 2025
SP - 795
EP - 800
BT - 2025 International Symposium of Electronics Design Automation, ISEDA 2025
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 9 May 2025 through 12 May 2025
ER -