TY - JOUR
T1 - Magnifier
T2 - A Chiplet Feature-Aware Test Case Generation Method for Deep Learning Accelerators
AU - Li, Boyu
AU - Zhu, Zongwei
AU - Liu, Weihong
AU - Cao, Qianyue
AU - Li, Changlong
AU - Ji, Cheng
AU - Li, Xi
AU - Zhou, Xuehai
N1 - Publisher Copyright:
© 1982-2012 IEEE.
PY - 2025
Y1 - 2025
N2 - The development of deep learning has led to increasing demands for computation and memory, making multichiplet accelerators a powerful solution. Multichiplet accelerators require more precise consideration of hardware configurations and mapping schemes in terms of computation, memory, and communication patterns compared to monolithic designs, in order to avoid underutilization of performance. However, there is currently a lack of performance testing methods specifically tailored for multichiplet accelerators. Existing testing methods primarily focus on correctness testing and do not address potential performance issues from a hardware perspective. To address these issues, this article proposes Magnifier: a test case generation method for performance testing of multichiplet accelerators. First, we analyze typical multichiplet accelerator prototype from the perspectives of computation, memory, and communication patterns, and summarize a chiplet feature-aware operator task set. Next, we define the test evaluation metric interdevice percentile performance standard deviation and use a candidate operator set to construct a sampling space for model-level test cases. Finally, we build a generative adversarial network to learn the distribution of high-diversity test cases, enabling the rapid generation of high-quality test cases. We validate the proposed method on both simulated and real multichiplet accelerators. Experiments show that Magnifier can improve the metric of test cases by up to 3.42 times and significantly reduce generation time, providing valuable insights for optimizing the hardware and software of multichiplet accelerators.
AB - The development of deep learning has led to increasing demands for computation and memory, making multichiplet accelerators a powerful solution. Multichiplet accelerators require more precise consideration of hardware configurations and mapping schemes in terms of computation, memory, and communication patterns compared to monolithic designs, in order to avoid underutilization of performance. However, there is currently a lack of performance testing methods specifically tailored for multichiplet accelerators. Existing testing methods primarily focus on correctness testing and do not address potential performance issues from a hardware perspective. To address these issues, this article proposes Magnifier: a test case generation method for performance testing of multichiplet accelerators. First, we analyze typical multichiplet accelerator prototype from the perspectives of computation, memory, and communication patterns, and summarize a chiplet feature-aware operator task set. Next, we define the test evaluation metric interdevice percentile performance standard deviation and use a candidate operator set to construct a sampling space for model-level test cases. Finally, we build a generative adversarial network to learn the distribution of high-diversity test cases, enabling the rapid generation of high-quality test cases. We validate the proposed method on both simulated and real multichiplet accelerators. Experiments show that Magnifier can improve the metric of test cases by up to 3.42 times and significantly reduce generation time, providing valuable insights for optimizing the hardware and software of multichiplet accelerators.
KW - Dataflow optimization
KW - generative adversarial network (GAN)
KW - multichiplet accelerators
KW - test case generation
UR - https://www.scopus.com/pages/publications/85215005391
U2 - 10.1109/TCAD.2025.3528358
DO - 10.1109/TCAD.2025.3528358
M3 - 文章
AN - SCOPUS:85215005391
SN - 0278-0070
VL - 44
SP - 2803
EP - 2816
JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IS - 7
ER -