TY - GEN
T1 - Machine-Learning Based Nonlinerity Correction for Coarse-Fine SAR-TDC Hybrid ADC
AU - Deng, Hao
AU - Fan, Qingjun
AU - Zhang, Runxi
AU - Chen, Jinghong
N1 - Publisher Copyright:
© 2020 IEEE.
PY - 2020/8
Y1 - 2020/8
N2 - This paper presents a backend machine learningbased nonlinearity calibration scheme for a coarse-fine two stage SAR-TDC hybrid ADC. Different from conventional approaches, the machine learning-based nonlinearity calibration scheme avoids the on-chip pseudonumber (PN) generator or complex, specific matrix operations in the digital domain backend process. The scheme utilizes a two-layer neural network to extract and compensate the bit-weight error caused by circuit nonlinearities such as inter-stage gain error or time-to-digital converter (TDC) delay cell mismatch. The neural network uses the ADC DNL and INL testing results as training data, thus avoiding additional reference channel or a split ADC structure. A 10-bit 500 MS/s coarse-fine SAR-TDC ADC is designed in 22nm FDSOI technology to validate the scheme. The simulation results show the ADC achieves an SNDR of 57 dB, SFDR of 71.3 dB, and an ENOB of 9.18 bits, corresponding to a Walden FOM of 5.2 fJ/conv.-step after backend nonlinearity calibration.
AB - This paper presents a backend machine learningbased nonlinearity calibration scheme for a coarse-fine two stage SAR-TDC hybrid ADC. Different from conventional approaches, the machine learning-based nonlinearity calibration scheme avoids the on-chip pseudonumber (PN) generator or complex, specific matrix operations in the digital domain backend process. The scheme utilizes a two-layer neural network to extract and compensate the bit-weight error caused by circuit nonlinearities such as inter-stage gain error or time-to-digital converter (TDC) delay cell mismatch. The neural network uses the ADC DNL and INL testing results as training data, thus avoiding additional reference channel or a split ADC structure. A 10-bit 500 MS/s coarse-fine SAR-TDC ADC is designed in 22nm FDSOI technology to validate the scheme. The simulation results show the ADC achieves an SNDR of 57 dB, SFDR of 71.3 dB, and an ENOB of 9.18 bits, corresponding to a Walden FOM of 5.2 fJ/conv.-step after backend nonlinearity calibration.
KW - Coarse-fine ADC architecture
KW - Machine learning-based nonlinearity correction
KW - SAR ADC
KW - Subrange TDC
UR - https://www.scopus.com/pages/publications/85090560944
U2 - 10.1109/MWSCAS48704.2020.9184523
DO - 10.1109/MWSCAS48704.2020.9184523
M3 - 会议稿件
AN - SCOPUS:85090560944
T3 - Midwest Symposium on Circuits and Systems
SP - 265
EP - 268
BT - 2020 IEEE 63rd International Midwest Symposium on Circuits and Systems, MWSCAS 2020 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 63rd IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2020
Y2 - 9 August 2020 through 12 August 2020
ER -