MAC: Migration-aware compilation for STT-RAM based hybrid cache in embedded systems

Qingan Li; Jianhua Li; Liang Shi; Chun Jason Xue; Yanxiang He

doi:10.1145/2333660.2333738

MAC: Migration-aware compilation for STT-RAM based hybrid cache in embedded systems

Qingan Li^*
, Jianhua Li
, Liang Shi
, Chun Jason Xue
, Yanxiang He

^*Corresponding author for this work

City University of Hong Kong
University of Science and Technology of China
Wuhan University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

33 Scopus citations

Abstract

Hybrid caches consisting of both STT-RAM and SRAM have been proposed recently for energy efficiency. To explore the advantages of hybrid cache, most work on hybrid caches employs migration based strategies to dynamically move write-intensive data from STT-RAM to SRAM. Migrations require additional read and write operations for data movement and may lead to significant overheads. To address this issue, this paper proposes a Migration-Aware Compilation (MAC) approach to improve the energy efficiency and performance of STT-RAM based hybrid cache. By re-arranging data layout, the data access pattern in memory blocks is changed such that the number of migrations is reduced without any hardware modification. The reduction of migration overheads in turn improves energy efficiency and performance. The experimental results show that with the proposed approach, on average, the number of write operations on STT-RAM is reduced by 13.4%, the number of migrations is reduced by 16.1%, the total dynamic energy is reduced by 8.5%, and the total latency is reduced by 12.1%.

Original language	English
Title of host publication	ISLPED'12 - Proceedings of the International Symposium on Low Power Electronics and Design
Pages	351-356
Number of pages	6
DOIs	https://doi.org/10.1145/2333660.2333738
State	Published - 2012
Externally published	Yes
Event	2012 ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED'12 - Redondo Beach, CA, United States Duration: 30 Jul 2012 → 1 Aug 2012

Publication series

Name	Proceedings of the International Symposium on Low Power Electronics and Design
ISSN (Print)	1533-4678

Conference

Conference	2012 ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED'12
Country/Territory	United States
City	Redondo Beach, CA
Period	30/07/12 → 1/08/12

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Keywords

compiler
hybrid cache
migration

Access to Document

10.1145/2333660.2333738

Cite this

@inproceedings{cfa4f1de211b494da80427feaa7bdeb0,

title = "MAC: Migration-aware compilation for STT-RAM based hybrid cache in embedded systems",

abstract = "Hybrid caches consisting of both STT-RAM and SRAM have been proposed recently for energy efficiency. To explore the advantages of hybrid cache, most work on hybrid caches employs migration based strategies to dynamically move write-intensive data from STT-RAM to SRAM. Migrations require additional read and write operations for data movement and may lead to significant overheads. To address this issue, this paper proposes a Migration-Aware Compilation (MAC) approach to improve the energy efficiency and performance of STT-RAM based hybrid cache. By re-arranging data layout, the data access pattern in memory blocks is changed such that the number of migrations is reduced without any hardware modification. The reduction of migration overheads in turn improves energy efficiency and performance. The experimental results show that with the proposed approach, on average, the number of write operations on STT-RAM is reduced by 13.4\%, the number of migrations is reduced by 16.1\%, the total dynamic energy is reduced by 8.5\%, and the total latency is reduced by 12.1\%.",

keywords = "compiler, hybrid cache, migration",

author = "Qingan Li and Jianhua Li and Liang Shi and Xue, \{Chun Jason\} and Yanxiang He",

year = "2012",

doi = "10.1145/2333660.2333738",

language = "英语",

isbn = "9781450312493",

series = "Proceedings of the International Symposium on Low Power Electronics and Design",

pages = "351--356",

booktitle = "ISLPED'12 - Proceedings of the International Symposium on Low Power Electronics and Design",

note = "2012 ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED'12 ; Conference date: 30-07-2012 Through 01-08-2012",

}

Li, Q, Li, J, Shi, L, Xue, CJ & He, Y 2012, MAC: Migration-aware compilation for STT-RAM based hybrid cache in embedded systems. in ISLPED'12 - Proceedings of the International Symposium on Low Power Electronics and Design. Proceedings of the International Symposium on Low Power Electronics and Design, pp. 351-356, 2012 ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED'12, Redondo Beach, CA, United States, 30/07/12. https://doi.org/10.1145/2333660.2333738

MAC: Migration-aware compilation for STT-RAM based hybrid cache in embedded systems. / Li, Qingan; Li, Jianhua; Shi, Liang et al.
ISLPED'12 - Proceedings of the International Symposium on Low Power Electronics and Design. 2012. p. 351-356 (Proceedings of the International Symposium on Low Power Electronics and Design).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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T2 - 2012 ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED'12

AU - Li, Qingan

AU - Li, Jianhua

AU - Shi, Liang

AU - Xue, Chun Jason

AU - He, Yanxiang

PY - 2012

Y1 - 2012

N2 - Hybrid caches consisting of both STT-RAM and SRAM have been proposed recently for energy efficiency. To explore the advantages of hybrid cache, most work on hybrid caches employs migration based strategies to dynamically move write-intensive data from STT-RAM to SRAM. Migrations require additional read and write operations for data movement and may lead to significant overheads. To address this issue, this paper proposes a Migration-Aware Compilation (MAC) approach to improve the energy efficiency and performance of STT-RAM based hybrid cache. By re-arranging data layout, the data access pattern in memory blocks is changed such that the number of migrations is reduced without any hardware modification. The reduction of migration overheads in turn improves energy efficiency and performance. The experimental results show that with the proposed approach, on average, the number of write operations on STT-RAM is reduced by 13.4%, the number of migrations is reduced by 16.1%, the total dynamic energy is reduced by 8.5%, and the total latency is reduced by 12.1%.

AB - Hybrid caches consisting of both STT-RAM and SRAM have been proposed recently for energy efficiency. To explore the advantages of hybrid cache, most work on hybrid caches employs migration based strategies to dynamically move write-intensive data from STT-RAM to SRAM. Migrations require additional read and write operations for data movement and may lead to significant overheads. To address this issue, this paper proposes a Migration-Aware Compilation (MAC) approach to improve the energy efficiency and performance of STT-RAM based hybrid cache. By re-arranging data layout, the data access pattern in memory blocks is changed such that the number of migrations is reduced without any hardware modification. The reduction of migration overheads in turn improves energy efficiency and performance. The experimental results show that with the proposed approach, on average, the number of write operations on STT-RAM is reduced by 13.4%, the number of migrations is reduced by 16.1%, the total dynamic energy is reduced by 8.5%, and the total latency is reduced by 12.1%.

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KW - migration

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ER -

MAC: Migration-aware compilation for STT-RAM based hybrid cache in embedded systems

Abstract

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UN SDGs

Keywords

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