TY - GEN
T1 - Loss is gain
T2 - 28th Great Lakes Symposium on VLSI, GLSVLSI 2018
AU - Di, Yejia
AU - Shi, Liang
AU - Gao, Congming
AU - Li, Qiao
AU - Wu, Kaijie
AU - Xue, Chun Jason
N1 - Publisher Copyright:
© 2018 Association for Computing Machinery.
PY - 2018/5/30
Y1 - 2018/5/30
N2 - Reliability has been a challenge in the development of NAND flash memory, due to its technology size scaling and bit density improvement. To ensure the data integrity, error correction codes (ECC) with high error correction capability have been suggested. However, much higher costs will be introduced which cannot be supported for cost-limited consumer-level flash memory. Thus, low-cost ECCs are usually applied. In this work, a reliability improvement scheme is proposed for low-cost ECC enabled consumer-level flash memory. The scheme is motivated by the finding that low-cost ECC is able to protect shortened encoded data with improved reliability. This is because that the less the encoded data are, the less the errors will be occurred. With this motivation, a design is proposed to construct the shortened data case for a low-cost ECC when it cannot be able to provide the reliability requirement. Second, two relaxation approaches are proposed to relax the space reduction as it has bad effects on flash memory. A model guided evaluation is finally presented, and the results show that the lifetime can be significantly improved with little space reduction.
AB - Reliability has been a challenge in the development of NAND flash memory, due to its technology size scaling and bit density improvement. To ensure the data integrity, error correction codes (ECC) with high error correction capability have been suggested. However, much higher costs will be introduced which cannot be supported for cost-limited consumer-level flash memory. Thus, low-cost ECCs are usually applied. In this work, a reliability improvement scheme is proposed for low-cost ECC enabled consumer-level flash memory. The scheme is motivated by the finding that low-cost ECC is able to protect shortened encoded data with improved reliability. This is because that the less the encoded data are, the less the errors will be occurred. With this motivation, a design is proposed to construct the shortened data case for a low-cost ECC when it cannot be able to provide the reliability requirement. Second, two relaxation approaches are proposed to relax the space reduction as it has bad effects on flash memory. A model guided evaluation is finally presented, and the results show that the lifetime can be significantly improved with little space reduction.
UR - https://www.scopus.com/pages/publications/85049468821
U2 - 10.1145/3194554.3194571
DO - 10.1145/3194554.3194571
M3 - 会议稿件
AN - SCOPUS:85049468821
T3 - Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI
SP - 225
EP - 230
BT - GLSVLSI 2018 - Proceedings of the 2018 Great Lakes Symposium on VLSI
PB - Association for Computing Machinery
Y2 - 23 May 2018 through 25 May 2018
ER -