TY - GEN
T1 - Loop Scheduling and Partitions for Hiding Memory Latencies
AU - Chen, Fei
AU - Sha, Edwin Hsing Mean
PY - 1999/11/1
Y1 - 1999/11/1
N2 - Partition Scheduling with Prefetching (PSP) is a memory latency hiding technique which combines the loop pipelining technique with data prefetching. In PSP, the iteration space is first divided into regular partitions. Then two parts of the schedule, the ALU part and the memory part, are produced and balanced to produce an overall schedule with high throughput. These two parts are executed simultaneously, and hence the remote memory latency are overlapped. We study the optimal partition shape and size so that a well balanced overall schedule can be obtained. Experiments on DSP benchmarks show that the proposed methodology consistently produces optimal or near optimal solutions.
AB - Partition Scheduling with Prefetching (PSP) is a memory latency hiding technique which combines the loop pipelining technique with data prefetching. In PSP, the iteration space is first divided into regular partitions. Then two parts of the schedule, the ALU part and the memory part, are produced and balanced to produce an overall schedule with high throughput. These two parts are executed simultaneously, and hence the remote memory latency are overlapped. We study the optimal partition shape and size so that a well balanced overall schedule can be obtained. Experiments on DSP benchmarks show that the proposed methodology consistently produces optimal or near optimal solutions.
UR - https://www.scopus.com/pages/publications/73449135115
M3 - 会议稿件
AN - SCOPUS:73449135115
T3 - Proceedings of the International Symposium on System Synthesis
BT - Proceedings of the 12th International Symposium on System Synthesis, ISSS 1999
PB - IEEE Computer Society
T2 - 12th International Symposium on System Synthesis, ISSS 1999
Y2 - 10 November 1999 through 12 November 1999
ER -