Loop scheduling and assignment to minimize energy while hiding latency for heterogeneous multi-bank memory

Meikang Qiu; Jiande Wu; Chun Jason Xue; Jingtong Aaron Hu; Wei Che Tseng; Edwin H.M. Sha

doi:10.1109/FPL.2008.4629983

Loop scheduling and assignment to minimize energy while hiding latency for heterogeneous multi-bank memory

Meikang Qiu^*
, Jiande Wu
, Chun Jason Xue
, Jingtong Aaron Hu
, Wei Che Tseng
, Edwin H.M. Sha

^*Corresponding author for this work

University of New Orleans
City University of Hong Kong
University of Texas at Dallas

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

Many high-performance DSP processors employ multi-bank on-chip memory to improve performance and energy consumption. This architectural feature supports higher memory bandwidth by allowing multiple data memory accesses to be executed in parallel. This paper studies the scheduling and assignment problem on minimizing the total energy consumption while satisfying timing constraint with heterogeneous multi-bank memory for applications with loop. An algorithm, TASL (Type Assignment and Scheduling for Loops), is proposed. The algorithm uses loop scheduling and assignment with the consideration of variable partition to find the best configuration for both memory and ALU.

Original language	English
Title of host publication	Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL
Pages	459-462
Number of pages	4
DOIs	https://doi.org/10.1109/FPL.2008.4629983
State	Published - 2008
Externally published	Yes
Event	2008 International Conference on Field Programmable Logic and Applications, FPL - Heidelberg, Germany Duration: 8 Sep 2008 → 10 Sep 2008

Publication series

Name	Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL

Conference

Conference	2008 International Conference on Field Programmable Logic and Applications, FPL
Country/Territory	Germany
City	Heidelberg
Period	8/09/08 → 10/09/08

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

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10.1109/FPL.2008.4629983

Cite this

Qiu, M., Wu, J., Xue, C. J., Hu, J. A., Tseng, W. C., & Sha, E. H. M. (2008). Loop scheduling and assignment to minimize energy while hiding latency for heterogeneous multi-bank memory. In Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL (pp. 459-462). Article 4629983 (Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL). https://doi.org/10.1109/FPL.2008.4629983

Qiu, Meikang ; Wu, Jiande ; Xue, Chun Jason et al. / Loop scheduling and assignment to minimize energy while hiding latency for heterogeneous multi-bank memory. Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL. 2008. pp. 459-462 (Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL).

@inproceedings{e6a9b23bf9a14080be9a00c3af46f8e9,

title = "Loop scheduling and assignment to minimize energy while hiding latency for heterogeneous multi-bank memory",

abstract = "Many high-performance DSP processors employ multi-bank on-chip memory to improve performance and energy consumption. This architectural feature supports higher memory bandwidth by allowing multiple data memory accesses to be executed in parallel. This paper studies the scheduling and assignment problem on minimizing the total energy consumption while satisfying timing constraint with heterogeneous multi-bank memory for applications with loop. An algorithm, TASL (Type Assignment and Scheduling for Loops), is proposed. The algorithm uses loop scheduling and assignment with the consideration of variable partition to find the best configuration for both memory and ALU.",

author = "Meikang Qiu and Jiande Wu and Xue, \{Chun Jason\} and Hu, \{Jingtong Aaron\} and Tseng, \{Wei Che\} and Sha, \{Edwin H.M.\}",

year = "2008",

doi = "10.1109/FPL.2008.4629983",

language = "英语",

isbn = "9781424419616",

series = "Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL",

pages = "459--462",

booktitle = "Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL",

note = "2008 International Conference on Field Programmable Logic and Applications, FPL ; Conference date: 08-09-2008 Through 10-09-2008",

}

Qiu, M, Wu, J, Xue, CJ, Hu, JA, Tseng, WC & Sha, EHM 2008, Loop scheduling and assignment to minimize energy while hiding latency for heterogeneous multi-bank memory. in Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL., 4629983, Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL, pp. 459-462, 2008 International Conference on Field Programmable Logic and Applications, FPL, Heidelberg, Germany, 8/09/08. https://doi.org/10.1109/FPL.2008.4629983

Loop scheduling and assignment to minimize energy while hiding latency for heterogeneous multi-bank memory. / Qiu, Meikang; Wu, Jiande; Xue, Chun Jason et al.
Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL. 2008. p. 459-462 4629983 (Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Loop scheduling and assignment to minimize energy while hiding latency for heterogeneous multi-bank memory

AU - Qiu, Meikang

AU - Wu, Jiande

AU - Xue, Chun Jason

AU - Hu, Jingtong Aaron

AU - Tseng, Wei Che

AU - Sha, Edwin H.M.

PY - 2008

Y1 - 2008

N2 - Many high-performance DSP processors employ multi-bank on-chip memory to improve performance and energy consumption. This architectural feature supports higher memory bandwidth by allowing multiple data memory accesses to be executed in parallel. This paper studies the scheduling and assignment problem on minimizing the total energy consumption while satisfying timing constraint with heterogeneous multi-bank memory for applications with loop. An algorithm, TASL (Type Assignment and Scheduling for Loops), is proposed. The algorithm uses loop scheduling and assignment with the consideration of variable partition to find the best configuration for both memory and ALU.

AB - Many high-performance DSP processors employ multi-bank on-chip memory to improve performance and energy consumption. This architectural feature supports higher memory bandwidth by allowing multiple data memory accesses to be executed in parallel. This paper studies the scheduling and assignment problem on minimizing the total energy consumption while satisfying timing constraint with heterogeneous multi-bank memory for applications with loop. An algorithm, TASL (Type Assignment and Scheduling for Loops), is proposed. The algorithm uses loop scheduling and assignment with the consideration of variable partition to find the best configuration for both memory and ALU.

UR - https://www.scopus.com/pages/publications/54949135289

U2 - 10.1109/FPL.2008.4629983

DO - 10.1109/FPL.2008.4629983

M3 - 会议稿件

AN - SCOPUS:54949135289

SN - 9781424419616

T3 - Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL

SP - 459

EP - 462

BT - Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL

T2 - 2008 International Conference on Field Programmable Logic and Applications, FPL

Y2 - 8 September 2008 through 10 September 2008

ER -

Qiu M, Wu J, Xue CJ, Hu JA, Tseng WC, Sha EHM. Loop scheduling and assignment to minimize energy while hiding latency for heterogeneous multi-bank memory. In Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL. 2008. p. 459-462. 4629983. (Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL). doi: 10.1109/FPL.2008.4629983

Loop scheduling and assignment to minimize energy while hiding latency for heterogeneous multi-bank memory

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