TY - GEN
T1 - LogicCraft
T2 - 7th IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2025
AU - Lin, Minwei
AU - Bui, Duy Hieu
AU - Wang, Chao
AU - Lu, Wangzilu
AU - Tang, Ruoyu
AU - Zhang, Qing
AU - Zhang, Yuhang
AU - Zhao, Jian
AU - Tran, Xuan Tu
AU - Li, Yongfu
N1 - Publisher Copyright:
© 2025 IEEE.
PY - 2025
Y1 - 2025
N2 - In digital integrated circuit (IC) design, the need for custom standard cells tailored to specific design constraints, such as power, area, and performance, is increasingly critical. This paper presents an approach that leverages Large Language Models (LLMs) to automate the translation and optimization of Boolean tables into custom pull-up networks, using established principles to generate complementary pull-down networks. The proposed methodology focuses on automated translation, optimization, and seamless integration into standard electronic design automation (EDA) workflows. By utilizing LLMs, this approach significantly reduces design time, enhances optimization, and minimizes human error. This makes it a powerful tool for improving the efficiency and effectiveness of custom standard cell design in digital logic circuits.
AB - In digital integrated circuit (IC) design, the need for custom standard cells tailored to specific design constraints, such as power, area, and performance, is increasingly critical. This paper presents an approach that leverages Large Language Models (LLMs) to automate the translation and optimization of Boolean tables into custom pull-up networks, using established principles to generate complementary pull-down networks. The proposed methodology focuses on automated translation, optimization, and seamless integration into standard electronic design automation (EDA) workflows. By utilizing LLMs, this approach significantly reduces design time, enhances optimization, and minimizes human error. This makes it a powerful tool for improving the efficiency and effectiveness of custom standard cell design in digital logic circuits.
KW - Large Language Model
KW - Logic Expression
KW - Optimization
KW - SPICE
KW - Standard Cell Design
UR - https://www.scopus.com/pages/publications/105018802127
U2 - 10.1109/AICAS64808.2025.11173139
DO - 10.1109/AICAS64808.2025.11173139
M3 - 会议稿件
AN - SCOPUS:105018802127
T3 - AICAS 2025 - 2025 7th IEEE International Conference on Artificial Intelligence Circuits and Systems, Proceedings
BT - AICAS 2025 - 2025 7th IEEE International Conference on Artificial Intelligence Circuits and Systems, Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 28 April 2025 through 30 April 2025
ER -