Linear and Resolution Adjusted On-Chip Aging Detection of NBTI Degradation

Accurate detection of nanometer CMOS circuits is one of the most critical issues for tolerating the negative bias temperature instability (NBTI). In this paper, a fully digital on-chip aging detector, which achieves a direct correlation between the threshold voltage degradation (Δ Vth) and the phase difference, has been proposed. The linear correlation is realized based on our revised Schmitt triggers in which the stressed and the fresh devices are embedded. Moreover, the readout circuit has been designed to count, lock, and output the samples through a parallel-to-serial converter. The main contributions include: 1) good linear correlation between Δ Vth and the pulse width is provided; 2) the measurement resolution can be adjusted by changing the input slope; and 3) the circuits are almost independent to process and voltage due to the symmetrical structure and layout matching. The prototype chip has been fabricated in a 1.1 V, 36-nm CMOS technology. The measured equivalent resolution is 3.4 ns/mV under 1 μs rise-time sawtooth input, which is sufficient to suppress the unwanted recovery. Compared with the traditional testing, the proposed detector can satisfy the surveillance of NBTI degradation. This flexible architecture can be easily revised to accommodate other aging mechanisms, such as PBTI and HCI.