Latency variation aware read performance optimization on 3D high density NAND flash memory

State-of-the-art high density NAND flash memory has been recommended as read intensive storage device due to their excellent read performance. However, recent studies and reports show that the read latency of high density NAND flash memory is increasing. The reason comes from at least two aspects: First, high density flash generally adopts multiple bits per cell technique, where the access latency of the most significant bits is largely increased. Second, due to the reliability variation among these bits, the access latency of the most significant bits is further increased. We introduce RLV, a read performance optimization scheme is proposed to exploit the read latency variation among the multiple bits. The basic idea is that firstly identify the hotness of read data and then move them to the places with corresponding read latency. Our evaluation shows that RLV incurs negligible overhead, while improving read performance by 14% on average compared with state-of-the-arts.