Large-scale chip layout pattern clustering method based on graph matching

In the integrated circuits field, the rapid and accurate detection of defects and anomalies is a critical factor in improving lithography process yields. Research on large-scale chip layout pattern feature extraction and clustering algorithms plays a crucial role in enhancing chip manufacturing yield and improving manufacturing processes. This paper proposes a graph matching-based clustering method, leveraging the high redundancy and relatively simple circuit structure of chip layout patterns. Our method innovatively employs a graph-based representation to capture keypoint information in layout patterns, applies dual-similarity constraints to ensure both node and edge similarities, and utilizes agglomerative hierarchical clustering to merge structurally similar patterns, reducing the reliance on typical values. These enhancements allow for better handling of complex geometries, thus improving the efficiency and stability of pattern clustering. Compared to traditional clustering methods based on image statistical characteristics, our approach considers the geometric constraints within the chip layout, achieving effective clustering on large-scale chip layout patterns.