Improving self-timed pipeline ring performance through the addition of buffer loops

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2 Scopus citations

Abstract

Researchers have looked for ways to improve the performance of self-timed pipelines by changing the communication scheme in an effort to reduce the communication delay. A proposed approach divides the total communication time into two parts: data communication delay and pace handshaking overhead. By adding buffer loops to each stage of a self-timed pipeline, the pace handshaking overhead is reduced, thus decreasing the total time spent on communication. One important result of this design innovation has been the simplification of analysis needed to find the best initial system configuration. In addition, the design has a lower average cycle time than traditional self-timed pipelines, which leads to an increase in performance.

Original languageEnglish
Pages (from-to)218-223
Number of pages6
JournalProceedings of the IEEE Great Lakes Symposium on VLSI
StatePublished - 1995
Externally publishedYes
EventProceedings of the 5th Great Lakes Symposium on VLSI - Buffalo, NY, USA
Duration: 16 Mar 199518 Mar 1995

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