TY - JOUR
T1 - Impact of Process Variation on Nanosheet Gate-All-Around Complementary FET (CFET)
AU - Yang, Xiaoqiao
AU - Li, Xianglong
AU - Liu, Ziyu
AU - Sun, Yabin
AU - Liu, Yun
AU - Li, Xiaojin
AU - Shi, Yanling
N1 - Publisher Copyright:
© 1963-2012 IEEE.
PY - 2022/7/1
Y1 - 2022/7/1
N2 - In this work, dc characteristic variations of nanosheet (NS) gate-all-around (GAA) complementary FET (CFET) induced by process fluctuations are investigated for the first time. Four process variability sources including work-function variation (WFV), line edge roughness (LER), gate edge roughness (GER), and random dopant fluctuation (RDF) are characterized. Compared to the conventional NA GAA FET, the differences mainly exist in GER. The electrostatic potential variation induced by GER in CFET is affected by both the common metal gate and the additional p-type work-function (p-WF) liner for p-FET. Therefore, the impact of GER on p-FET is much larger than n-FET as well as conventional NS GAA FET. Thickening the p-WF liner is proposed to overcome the drawback. Calculated overall variations considering all process fluctuation sources are also discussed, highlighting the impact of the dual-WF gate on p-FET. The results are helpful for the characterization and optimization of variations in CFET and precise CFET-based circuit design.
AB - In this work, dc characteristic variations of nanosheet (NS) gate-all-around (GAA) complementary FET (CFET) induced by process fluctuations are investigated for the first time. Four process variability sources including work-function variation (WFV), line edge roughness (LER), gate edge roughness (GER), and random dopant fluctuation (RDF) are characterized. Compared to the conventional NA GAA FET, the differences mainly exist in GER. The electrostatic potential variation induced by GER in CFET is affected by both the common metal gate and the additional p-type work-function (p-WF) liner for p-FET. Therefore, the impact of GER on p-FET is much larger than n-FET as well as conventional NS GAA FET. Thickening the p-WF liner is proposed to overcome the drawback. Calculated overall variations considering all process fluctuation sources are also discussed, highlighting the impact of the dual-WF gate on p-FET. The results are helpful for the characterization and optimization of variations in CFET and precise CFET-based circuit design.
KW - Complementary FET (CFET)
KW - gate edge roughness (GER)
KW - line edge roughness (LER)
KW - process fluctuation
KW - random dopant fluctuation (RDF)
KW - work-function variation (WFV)
UR - https://www.scopus.com/pages/publications/85131765970
U2 - 10.1109/TED.2022.3176835
DO - 10.1109/TED.2022.3176835
M3 - 文章
AN - SCOPUS:85131765970
SN - 0018-9383
VL - 69
SP - 4029
EP - 4036
JO - IEEE Transactions on Electron Devices
JF - IEEE Transactions on Electron Devices
IS - 7
ER -