TY - JOUR
T1 - Impact of Geometry, Doping, Temperature, and Boundary Conductivity on Thermal Characteristics of 14-nm Bulk and SOI FinFETs
AU - Sun, Junya
AU - Li, Xiaojin
AU - Sun, Yabin
AU - Shi, Yanling
N1 - Publisher Copyright:
© 2001-2011 IEEE.
PY - 2020/3
Y1 - 2020/3
N2 - In this paper, the self-heating effect (SHE) in 14-nm bulk and SOI FinFETs are investigated through the TCAD simulation. To achieve high authoritative evidences, the calibration is performed by {I} _{\mathrm{ D}} - {V} _{\mathrm{ G}} curve fitting based on the experimental data. The main contributions include: 1) The distribution of heat generation and temperature gradient along the channel are disclosed. Two peeks of heat generation are observed in source extension (SE) and drain extension (DE), respectively; 2) The dependence of maximum lattice temperature and thermal resistance on device geometry and parameters including fin width, fin height, length of SE and DE, the thickness of STI and BOX, doping concentration of extension, and gate voltage, are thoroughly analyzed; 3) The influence of SHEs on the electrical characteristic of FinFET under different ambient temperatures are also revealed. Moreover, the critical heat removal paths of bulk and SOI FinFETs are discussed. For the former, most of heat vertically diffuses to the substrate, and then to heat sink, whereas in SOI FinFET it firstly dissipates to source, drain, and gate, and then to heat sink. Finally, several optimization thumbs of SHEs are proposed.
AB - In this paper, the self-heating effect (SHE) in 14-nm bulk and SOI FinFETs are investigated through the TCAD simulation. To achieve high authoritative evidences, the calibration is performed by {I} _{\mathrm{ D}} - {V} _{\mathrm{ G}} curve fitting based on the experimental data. The main contributions include: 1) The distribution of heat generation and temperature gradient along the channel are disclosed. Two peeks of heat generation are observed in source extension (SE) and drain extension (DE), respectively; 2) The dependence of maximum lattice temperature and thermal resistance on device geometry and parameters including fin width, fin height, length of SE and DE, the thickness of STI and BOX, doping concentration of extension, and gate voltage, are thoroughly analyzed; 3) The influence of SHEs on the electrical characteristic of FinFET under different ambient temperatures are also revealed. Moreover, the critical heat removal paths of bulk and SOI FinFETs are discussed. For the former, most of heat vertically diffuses to the substrate, and then to heat sink, whereas in SOI FinFET it firstly dissipates to source, drain, and gate, and then to heat sink. Finally, several optimization thumbs of SHEs are proposed.
KW - FinFET
KW - Self-heating effects (SHE)
KW - TCAD
KW - electrothermal
KW - silicon on insulator (SOI)
UR - https://www.scopus.com/pages/publications/85082121349
U2 - 10.1109/TDMR.2020.2964734
DO - 10.1109/TDMR.2020.2964734
M3 - 文章
AN - SCOPUS:85082121349
SN - 1530-4388
VL - 20
SP - 119
EP - 127
JO - IEEE Transactions on Device and Materials Reliability
JF - IEEE Transactions on Device and Materials Reliability
IS - 1
M1 - 8951282
ER -