Impact of channel and spacer engineering on DC and RF performance of Gate-all-around FET

Zhen Zhou, Ya Bin Sun, Xiao Jin Li, Yan Ling Shi, Shou Mian Chen, Shao Jian Hu, Ao Guo

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

In this paper, the insight to the impact of channel and spacer design on DC and RF performance of GAAFET is carried out. The channel design includes the optimization of effective channel lengths with overlap or underlap structure. Three kinds of spacer solutions are proposed and compared. Results show that this is a trade-off between RF performance and DC characteristics for any given design strategy. An appropriate overlap structure and dual-k spacer are found to provide superior RF performance, without obvious degradation in DC characteristics. The obtained results here are of great importance to guide the design of GAAFET into sub-10 nm technology node.

Original languageEnglish
Title of host publication2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2018 - Proceedings
EditorsTing-Ao Tang, Fan Ye, Yu-Long Jiang
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781538644409
DOIs
StatePublished - 5 Dec 2018
Event14th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2018 - Qingdao, China
Duration: 31 Oct 20183 Nov 2018

Publication series

Name2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2018 - Proceedings

Conference

Conference14th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2018
Country/TerritoryChina
CityQingdao
Period31/10/183/11/18

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