Abstract
Closely spaced, through-wafer interconnects are of large interest in RF MEMS and MEMS packaging. In this paper, a suitable technique to realize large arrays of small size through-wafer holes is presented. This approach is based on macroporous silicon formation in combination with wafer thinning. Very high aspect ratio (≥ 100) structures are realized. The wafers containing the large arrays of 2-3μm wide holes are thinned down to 200-150μm by lapping and polishing. Copper electroplating is finally employed to realize arrays of high aspect ratio Cu plugs.
| Original language | English |
|---|---|
| Pages | 634-637 |
| Number of pages | 4 |
| State | Published - 2003 |
| Externally published | Yes |
| Event | IEEE Sixteenth Annual International Conference on Micro Electro Mechanical Systems - Kyoto, Japan Duration: 19 Jan 2003 → 23 Jan 2003 |
Conference
| Conference | IEEE Sixteenth Annual International Conference on Micro Electro Mechanical Systems |
|---|---|
| Country/Territory | Japan |
| City | Kyoto |
| Period | 19/01/03 → 23/01/03 |