Fringe gate capacitance model for nanowire reconfigurable field effect transistors

In this work, an analytical model for the fringe gate capacitance in nanowire reconfigurable field effect transistors (RFETs) is proposed to address the increasing complexity of advanced RFET designs. The model's accuracy is validated using the 3-D field solver ensuring reliable performance predictions. To enhance the precision of the model, empirical parameters are incorporated into the model for different components of the nanowire structure. These parameters are designed to calibrate the effective width of ring-shaped capacitors and correct errors in electric field line distribution. The impact of device parameter variations on the overall fringe gate capacitance and model accuracy was evaluated with the root mean square error (RMSE) within 2.18 % error compared to the simulation values. The parasitic capacitance model can be embedded into machine learning-extracted RFET circuits to further simulate its impact on circuit performance. Results indicate that parasitic capacitance significantly increases circuit delay by up to 20.9 %. These findings underscore the importance of accurately modeling fringe gate capacitance in optimizing RF transistor circuit designs to enhance performance.