Formalising VERILOG

He Jifeng; Zhu Huibiao

doi:10.1109/ICECS.2000.911568

Formalising VERILOG

He Jifeng^*
, Zhu Huibiao

^*Corresponding author for this work

Software Engineering Institute

United Nations University Institute in Macau

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

27 Scopus citations

Abstract

This paper defines a non-trivial subset of VERILOG using a Plotkin-style operational semantics. We discuss the algebraic properties of programs based on the notion of bisimulation.

Original language	English
Title of host publication	ICECS 2000 - 7th IEEE International Conference on Electronics, Circuits and Systems
Pages	412-415
Number of pages	4
DOIs	https://doi.org/10.1109/ICECS.2000.911568
State	Published - 2000
Event	7th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2000 - Jounieh, Lebanon Duration: 17 Dec 2000 → 20 Dec 2000

Publication series

Name	Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems
Volume	1

Conference

Conference	7th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2000
Country/Territory	Lebanon
City	Jounieh
Period	17/12/00 → 20/12/00

Access to Document

10.1109/ICECS.2000.911568

Cite this

@inproceedings{99c963c2230d493691cc5880a0b6f34b,

title = "Formalising VERILOG",

abstract = "This paper defines a non-trivial subset of VERILOG using a Plotkin-style operational semantics. We discuss the algebraic properties of programs based on the notion of bisimulation.",

author = "He Jifeng and Zhu Huibiao",

year = "2000",

doi = "10.1109/ICECS.2000.911568",

language = "英语",

isbn = "0780365429",

series = "Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems",

pages = "412--415",

booktitle = "ICECS 2000 - 7th IEEE International Conference on Electronics, Circuits and Systems",

note = "7th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2000 ; Conference date: 17-12-2000 Through 20-12-2000",

}

Jifeng, H & Huibiao, Z 2000, Formalising VERILOG. in ICECS 2000 - 7th IEEE International Conference on Electronics, Circuits and Systems., 911568, Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, vol. 1, pp. 412-415, 7th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2000, Jounieh, Lebanon, 17/12/00. https://doi.org/10.1109/ICECS.2000.911568

TY - GEN

T1 - Formalising VERILOG

AU - Jifeng, He

AU - Huibiao, Zhu

PY - 2000

Y1 - 2000

N2 - This paper defines a non-trivial subset of VERILOG using a Plotkin-style operational semantics. We discuss the algebraic properties of programs based on the notion of bisimulation.

AB - This paper defines a non-trivial subset of VERILOG using a Plotkin-style operational semantics. We discuss the algebraic properties of programs based on the notion of bisimulation.

UR - https://www.scopus.com/pages/publications/0001543396

U2 - 10.1109/ICECS.2000.911568

DO - 10.1109/ICECS.2000.911568

M3 - 会议稿件

AN - SCOPUS:0001543396

SN - 0780365429

SN - 9780780365421

T3 - Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

SP - 412

EP - 415

BT - ICECS 2000 - 7th IEEE International Conference on Electronics, Circuits and Systems

T2 - 7th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2000

Y2 - 17 December 2000 through 20 December 2000

ER -

Formalising VERILOG

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