TY - JOUR
T1 - Flexible Zero-Copy IPC for Processing Chains in ROS 2
AU - Luo, Xiantong
AU - Jiang, Xu
AU - Liang, Haochun
AU - Tang, Yue
AU - Guan, Nan
AU - Yi, Wang
N1 - Publisher Copyright:
© 1982-2012 IEEE.
PY - 2025
Y1 - 2025
N2 - As ROS 2 becomes increasingly adopted in safety-critical real-time systems, the performance of its communication layer, especially inter-process communication (IPC), has emerged as a key bottleneck. While intra-process communication benefits from zero-copy transmission, IPC suffers from significant latency due to serialization and memory copying. Existing shared memory approaches offer limited support for ROS 2 applications, as they impose strict constraints on message formats (e.g., requiring statically sized, POD-compatible types) and overlook end-to-end communication across multi-stage pipelines. In this work, we propose a novel and flexible architecture for enabling zero-copy IPC in ROS 2. Our design supports dynamically structured and non-POD message types, integrates seamlessly with the existing communication framework, and requires no modification to application logic. It consists of a Mini Memory Management System (MMS) for shared memory handling and a Message Propagation Adapter (MPA) that ensures compatibility with the ROS 2 communication framework. Our experimental results show that our method significantly reduces communication latency and supports efficient end-to-end message propagation.
AB - As ROS 2 becomes increasingly adopted in safety-critical real-time systems, the performance of its communication layer, especially inter-process communication (IPC), has emerged as a key bottleneck. While intra-process communication benefits from zero-copy transmission, IPC suffers from significant latency due to serialization and memory copying. Existing shared memory approaches offer limited support for ROS 2 applications, as they impose strict constraints on message formats (e.g., requiring statically sized, POD-compatible types) and overlook end-to-end communication across multi-stage pipelines. In this work, we propose a novel and flexible architecture for enabling zero-copy IPC in ROS 2. Our design supports dynamically structured and non-POD message types, integrates seamlessly with the existing communication framework, and requires no modification to application logic. It consists of a Mini Memory Management System (MMS) for shared memory handling and a Message Propagation Adapter (MPA) that ensures compatibility with the ROS 2 communication framework. Our experimental results show that our method significantly reduces communication latency and supports efficient end-to-end message propagation.
KW - Communication Latency
KW - Inter-process Communication (IPC)
KW - Real-Time
KW - ROS 2
UR - https://www.scopus.com/pages/publications/105025476434
U2 - 10.1109/TCAD.2025.3644283
DO - 10.1109/TCAD.2025.3644283
M3 - 文章
AN - SCOPUS:105025476434
SN - 0278-0070
JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ER -